Jitter solution

[solderdude]

PLL's are actually used to lock on incoming frequencies and make the oscillator match that (in frequency and phase). The clock in most cases is a divided master clock and thu smultiply the incoming SPDIF clock and do this phase locked.
The reason for using that is to prevent buffer over- and under-run and so different frequencies (44.1 and 48kHz multiples) can be synced to different internal clocks.

I have explained the clock synchronizing thing above.

The 3 PLLs will also have jitter and depending on the kind of jitter certain amounts of jitter may well be 'averaged' a bit.
As I have explained before. The jitter of a DAC is not caused by the master clock but by other circuits and any decent DAC with jitter reduction circuits (on the input where jitter is a potential issue) is already below thresholds.

It is similar to believing SINAD 123 is better than SINAD 120. From a measurement p.o.v. it is but from a practical (audible) standpoint it is not.

 

[Hayabusa]

PLL's are actually used to lock on that, and multiply the incoming SPDIF clock and do this phase locked.
The reason for using that is to prevent buffer over- and under-run and so different frequencies (44.1 and 48kHz multiples) can be synced to different internal clocks.

I have explained the clock synchronizing thing above.

Yes I thought the OP was thinking about this application.
If your master clock for D/A is inside your device jitter is anyhow less of an issue (if not none at all)
Question now is can I combine N PLL locked clocks in such a way the jitter is lower.

 

[voodooless]

I thought the experiment was as this:
1 clock to synchronize to (for instance the SPDIF clock)
N pll's that lock to that.
Then some circuit that combines these N clocks.

A PLL is basically a variable clock with a circuit to sync it to another. You can do this in such a way that the output clock signal has lower jitter than one input. Why would you need three? Just make a singe better one.

 

[solderdude]

Yes I thought the OP was thinking about this application.
If your master clock for D/A is inside your device jitter is anyhow less of an issue (if not none at all)
Question now is can I combine N PLL locked clocks in such a way the jitter is lower.

It would only lower certain types of random jitter and not data related jitter which in general (SPDIF) is the biggest contributor.
For that there are jitter reduction circuits and tricks to make a PLL lock faster or weighted in a certain way.
This will not change even when using a 1000 PLLs and averaging its clock output.
Maybe, if one weighted (filtered) the correction signal to the VCO of the used PLLs (so they all react slightly differently) some type of jitter may be reduced a bit more than if you did not. The issue is that jitter is NOT an audible issue with any decently designed device now and well below any audible limits.

Its like the SINAD or noise floor race. Fun for the numbers game and fame of the brand making the lowest number but totally inconsequential in practice.

One MUST realize that there is not just 1 type of jitter and that 1 number characterizes the jitter.
Chasing jitter is equivalent to chasing SINAD. Both are just a number derived under certain circumstances and have to become really poor to become an audible issue.

Also ... there are very smart people specialized in this particular field of science (I am certainly not one of them) that make it their business to improve various aspects of clock generation and they would not be smart enough to just grab a pair of PLLs or sync clocks to create a better clock... one that is affordable and can be used in audio gear ?
Jitter reduction has to be performed by data receivers not so much the master clocks.
Of course there are many different qualities of clock generators and some will be measurable better. Price is a factor when mass producing clock generators and when building higher end DACs one can choose more expensive ones that may excel at certain properties.
Stability (done with temp control for instance, resulting in less drift) or lower phase noise or 'steeper' dV/dt or higher output voltage or higher PSRR but again... that's not where the 'jitter issue' lies with DAC devices.

 

[voodooless]

We’ve seen all kinds of DAC reviews from products that claim magical jitter performance, and in reality, none of them show more exceptional performance than some $80 DACs.

 

[solderdude]

That may well be because jitter is usually only measured with a specific type of signal (J-test) which is just a specific test method testing just a specific aspect though.
It is a bit like a SINAD test that is just measured at 1kHz and at a specific level.
Sure it says a lot but does not test for all types of jitter and has no audibility weighting in it.

 

[voodooless]

Well, for what it’s worth, none of those companies back up their claims either. And we’ve also seen examples where j-test performs worse. I’m inclined to think it’s all nonsense until they prove otherwise.

 

[mocenigo]

Because you call it “solution”. This implies there is a problem in the first place.

I got banned on DIYaudio (where I made some useful diy contributions) because I argued with somebody that insisted on closed phase loop jitter at -140Db being a real and easily audible problem - somebody that apart from such claims has never contributed to something, but this guy is a forum donor so… I got shafted.

 

[voodooless]

I got banned on DIYaudio (where I made some useful diy contributions) because I argued with somebody that insisted on closed phase loop jitter at -140Db being a real and easily audible problem - somebody that apart from such claims has never contributed to something, but this guy is a forum donor so… I got shafted.

It's not behavior that I commonly associate with DIYAudio, on the other hand, it's not totally surprising. It's one of the reasons that I'd rather go here than to DIYAudio even for DIY knowledge. You can have hundreds of pages of posts on the best compression driver and almost zero objective data. I find it rather useless and tiresome to wade through the murky waters of subjective opinions. And this is common all over the place. And it's sad really, because there are quite a number of very knowledgeable people there.

 

[mcdn]

I thought the experiment was as this:
1 clock to synchronize to (for instance the SPDIF clock)
N pll's that lock to that.
Then some circuit that combines these N clocks.

A clock is a device that gives an accurate view of how much time has passed. The output from it may have jitter but that’s got nothing to do with its accuracy as a clock.

A timing signal is a regular pulse that is used to synchronise the data sender and acquirer at both ends of a digital link. In audio we actually don’t care about the clock, only the timing. If your streamer runs a bit fast, your DAC shouldn’t care. This is why DACs just use the actual timing of the data to derive the timing signal. Good DACs therefore have essentially no jitter.

 

[DonH56]

I spent 12 years in the Advanced Technology Center of an aerospace company designing very low jitter clock oscillators and making literally multiple thousands of phase noise measurements using an Agilent 5052. I too hesistate to make forum replies because of the attitude and bias of many of the people who reply here, unless it's a very simple topic that can be verified by a link to a wiki entry. It's just not worth it.

Sounds like we have very similar backgrounds, or at least starting out I was working for an aerospace company designing custom analog ICs for radar systems. Mainly data converters, which led to all kinds of R&D for clock circuits, power circuits, various amplifiers, etc. Later I went deeper into the R&D side, still engineering and not pure science, which was a lot of fun but less likely to end up in production. Ended testing the analog side of high-speed serial links (PCIe/SAS/SATA etc.) but retired before PCIe6 -- I was looking forward to that, as PAM4 is fun stuff. Way easier than some of the other transmission schemes I worked with, but more than two levels.

Posting technical stuff here is a landmine... Either you're in disagreement with the accepted subjective norm and down the rabbit hole of endless argument, or an idiot for not going deep enough into the details since we have so many experts around. I try to hit a happy medium that most folk can understand without getting too technical. But, dance on a knife edge, you're going to get cut. I'm sort of tired of bleeding.

 

[fpitas]

I try to hit a happy medium that most folk can understand without getting too technical. But, dance on a knife edge, you're going to get cut. I'm sort of tired of bleeding.

I post as much as my patience allows. At the end of the day, if people are going to snipe and argue with me, they're also going to pay my rates.

 

[MAB]

Sounds like we have very similar backgrounds, or at least starting out I was working for an aerospace company designing custom analog ICs for radar systems. Mainly data converters, which led to all kinds of R&D for clock circuits, power circuits, various amplifiers, etc. Later I went deeper into the R&D side, still engineering and not pure science, which was a lot of fun but less likely to end up in production.

Posting technical stuff here is a landmine... Either you're in disagreement with the accepted subjective norm and down the rabbit hole of endless argument, or an idiot for not going deep enough into the details since we have so many experts around. I try to hit a happy medium that most folk can understand without getting too technical. But, dance on a knife edge, you're going to get cut. I'm sort of tired of bleeding.

I love your posts, they are very authentic. I understand your pain. Some topics are difficult to post on here, oddly the subjects I am comfortable and knowledgeable are the worst because of the voices of a few members here who are experts on everything and students of nothing.

 

[fpitas]

a few members here who are experts on everything and students of nothing

I just wish I knew if they are sincere. Sometimes my cynical side thinks that 99% is just subtle trolling.

 

[DonH56]

Sometimes it feels like this:

Does making off-topic posts cause thread jitter?

 

[mike7877]

why would solutions you try to invent help there if you do not have any deep understanding of the mechanisms behind it.

Many ideas and practical solutions come from people who don't have a comprehensive understanding of all the underlying mechanisms of what they're working on. In fact, there are entire professions which only deal with top level. Of course I wouldn't say it's optimal -they definitely would be more successful with a more complete understanding (come to the solution faster, come to more solutions, come to a solution at all...), but if we threw out everything that's been come up with by people without comprehensive understandings of of all the underlying mechanisms of whatever it is they were working on, we'd be short a lot of ideas....

 

[mike7877]

The jitter of a DAC is not caused by the master clock but by other circuits

See I didn't even know this... So really, past a point, the clock's jitter doesn't matter. Are these circuits a part of the DAC IC?

 

[mike7877]

This does not help jitter at all it would just mean that from the moment the circuit came online the slower one would be ignored.

The idea was that slower and faster would be ignored... I thought that's how I arranged things, but you say not. Is there a way to arrange the counter and clocks for this to be the case?

I have another idea, too, but it requires more clocks - say 20 (shouldn't be too much of a problem with how small things are, they could all be on one $1 chip

All clocks running with their outputs averaged, and periodically the averaged output is used to re-sync all clocks. This period has to be short enough that the clocks can't fall more than say a quarter cycle out of sync. The output is counted as a cycle when the voltage starts to fall. This could easily be as stupid as idea 1, I'm just putting it out there because the discussion is already happening.
edit: and these clocks are running much faster as well, say 1000x (like the first example for consistency)

 

[solderdude]

The idea was that slower and faster would be ignored... I thought that's how I arranged things, but you say not

When they are sync'd one will not be slower or faster and this aspect has nothing to do with jitter.

See I didn't even know this... So really, past a point, the clock's jitter doesn't matter. Are these circuits a part of the DAC IC?

Part of the receiver.

All clocks running with their outputs averaged,

Does not work as clocks would be beating and phase differing so mixing as well as digital this is not possible.
And when you sync them there is no benefit at all either between 2 or 200.
As said, the clock itself is not the biggest issue nor an audible issue.

 

[mike7877]

As said, the clock itself is not the biggest issue nor an audible issue.

Yes, I know. I acknowledged this

When they are sync'd one will not be slower or faster and this aspect has nothing to do with jitter.

The cycle coming sooner or later than expected is what I meant by slower and faster - jitter. I didn't word it well lol