- Thread Starter
- #21
Again.... jitter would then still be determined by the clock everything is locked to.
I see no benefits, just a lot of complexity that still has drift and stability of the master clock and the jitter of the 3 PLL's that are then averaged just a little.
I have not seen clock circuits employing this strategy.
Jitter in practice is caused by the way digital signals are transported and steepness of the many gates in the total circuit etc.
The comparator would be a counter, not a clock
edit: plus what I put in post 23.
It's just an idea... I do expect to be wrong or for there to be a reason why it's not implemented. But in the off chance there's not, why keep it to myself, yanno?
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