Sorry for being unclear. All measurements were conducted with AP-balanced input (200kohm) and no load.Is that loaded with 32ohm ?
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Sorry for being unclear. All measurements were conducted with AP-balanced input (200kohm) and no load.Is that loaded with 32ohm ?
The box containing the dummy load was not found. I didn't have time so I gave up.That'll change the phase considerably in the lows, assuming the coupling cap is directly at the output.
Most folks will load that dongle with something between 16ohm and 50ohm.
600ohm will be too high but arguably is better than 200k or even 10k.
33 ohm (standard value) makes the most sense.
got it. Well, thanks to that I was able to find the dummy load.@nagster then in that case no need to bother with more testing.
It does show that a gradual phase shift of 40degrees (-3 dB) @ 2Hz, that arguably is inaudible, has a quite severe effect on nulling and number generation when small and gradual phase shifts is not corrected for in the generation of a single number that is supposed to represent 'audio quality'.
I was just looking at the settings for the ADI-2 DAC and found that it was set to Ref 13dBu instead of Ref 7dBu.Phase measurement of 9038D.
I don't have a Shanling device.
* All measurements were conducted with AP balanced input (200kohm) and no load.
#9038 DFwf(median): -32.37 dB | #9038 DFmg(median): -45.49 dB | #9038 DFph(median): -34.84 dB |
M0 DFwf(median): -75.81 dB | M0 DFmg(median): -75.58 dB | M0 DFph(median): -61.53 dB |
I don't know exactly how various phase shifts are perceived by the ear and I also - as many - think that the low-freq phase shift is not too important. But I also know that if we replace all the phases of some music signal with the random ones, we will get just a noise shaped according to a freq content of the initial signal. In other words, audibility of phase errors has its thresholds/limits, should be characterized and hardly researched well with real music.
The magnitude DF is weighing everything except the phase error.What you should do is remove that phase error from the weighing of the 'sound quality' aspect.
In archimago's test of this unit, he mentioned that it uses 9038's builtin oscillator. So there supposed to be less possibilty it suffers from clock syncing issue. Anyway in ESS 9038 spec sheet, there's this:The resultant frequency variation causes a pernicious deterioration in perceived pitch stability, without delivering an apparent degradation in standard audio performance parameters such as THD+N when measured with conventional techniques.
BTW, RME's newest 2/4 pro does a wonderful job in This comparison.Is it possible, that this phenomenon will distort measurements of another DUT in the case of RME Adi-2 Pro FS R BE?
I doubt it. Like most any recent design, this is an asynchronous (UAC2) job. If it were to perform sample rate gymnastics as shown, this would be quite obvious in the jitter department.Could it be 'Frequency stability' mentioned here?
DPLL bandwidth is not generally an issue in USB devices. It becomes relevant when paired with S/P-DIF receivers of a relatively large PLL bandwidth, notoriously when manufacturers had to switch from AKM to older Cirrus parts post AKM factory fire.In archimago's test of this unit, he mentioned that it uses 9038's builtin oscillator. So there supposed to be less possibilty it suffers from clock syncing issue. Anyway in ESS 9038 spec sheet, there's this:
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Thanks for reply. I don't have any hardware background, things I can tell from what I read in edn.com is that asynchronous mode is usb audio implementation. Protocol underlying it is usb isochronous mode which doesn't have retransformation. And I think by asynchronous mode, it means USB dac as clock master asks for how many samples it needs from host. But if dac's own clock is inaccurate, it sees the sample rate it requests as objective clock and neither host or device sees it as an issue. I don't know about jitter test but is it detectable as jitter? Maybe someone repeat the test in edn and shows us the correlation between jitter test and it. Or perhaps only DF test can do it?I doubt it. Like most any recent design, this is an asynchronous (UAC2) job. If it were to perform sample rate gymnastics as shown, this would be quite obvious in the jitter department.
DPLL bandwidth is not generally an issue in USB devices. It becomes relevant when paired with S/P-DIF receivers of a relatively large PLL bandwidth, notoriously when manufacturers had to switch from AKM to older Cirrus parts post AKM factory fire.