Async clock mode or Sync for SPDIF?

[Mat]

Or maybe I should have named this thread "fixed vs DIR block" clock, but my question is which is the technically superior option to select?

On my SMSL D1, there are options for Async ("Master Clock fixed to 100Mhz") and Sync ("Master Clock comes from the DIR block" on the dac chip). With one jittery SPDIF source, Async is unlistenable and it can't hold a lock (similar to how Topping dacs behaved), but on another streamer (which doesn't measure like crap) both options work - but which is preferred? (all things being equal)

On the face of things the names sound reversed, with sync instead buffering the source through the DIR block and cleaning it up, while async is just running the source clock as is. Does that make Sync superior, or should Async be used and avoid the DIR block if possible?

 

[amirm]

I don't see how async is going to work as with clock drift, it will eventually lose sync (buffer over or underrun) causing a hiccup. So i would go for sync.

 

[onlyoneme]

What is "DIR block"? I've heard about DIR lock, but not about DIR block...
It's still about locking to the incoming clock with PLL?

 

[mdsimon2]

Imagine async is using the ASRC in the ESS DAC and sync is using the clock derived from SPDIF with no ASRC.

I would have thought async would be better in terms of locking to a jittery source, but it may be that the default DPLL bandwidth is too narrow.

The obvious answer is to use the option that works with your source . My understanding is that using an ASRC with a local oscillator is a superior approach to clocking from SPDIF in terms of jitter as described in this thread -> https://www.diyaudio.com/community/threads/asynchronous-sample-rate-conversion.28814/.

I don't think either approach should have clock drift issues as both will be sync'd to your source.

Michael

 

[amirm]

Imagine async is using the ASRC in the ESS DAC and sync is using the clock derived from SPDIF with no ASRC.

I don't think so. These are the settings for their digital PLL which is separate from the DAC chip.

 

[onlyoneme]

Isn't it reclocked by Altera FPGA?

 

[mdsimon2]

I don't think so. These are the settings for their digital PLL which is separate from the DAC chip.

What are you basing that on?

The manual screenshot the OP posted says it is setting the clock mode of the ES9038PRO. The ESS datasheet describes the difference between async and sync modes.

Michael

 

[amirm]

What are you basing that on?

Here you go:

 

[mdsimon2]

Here you go:

Can you expand upon how you think they are actually using this, specifically with regards to a SPDIF source? I understand this may be difficult/impossible given the poor documentation.

My guess is they have two audio frequency clocks, say 49.152/45.158 Mhz. When used with a USB input in SYNC mode these clocks are used to clock the ES9038PRO DAC and the data coming out of the XMOS is synchronous with the DAC clock. When used with a SPDIF input in SYNC mode I imagine these oscillators are not used and like the manual screenshot says a recovered clock from the DIR is used to clock the DAC. In all cases in SYNC mode the data being received by the DAC is synchronous to the clock being used.

I bet they have a third 100 MHz clock which is only used in ASYNC mode. In this mode the ES9038PRO is clocked by this oscillator which is operating asynchronously to the data being received (whether from USB or SPDIF) and therefore the jitter eliminator (ASRC) is used.

Michael

 

[Mat]

The obvious answer is to use the option that works with your source .

Normally, yeah for sure. Just in this case I was swapping some components around and for the one where both modes worked, was curious which was the better default

A lot of this terminology is going over my head though, so I guess....sync is best? heh

 

[mdsimon2]

Normally, yeah for sure. Just in this case I was swapping some components around and for the one where both modes worked, was curious which was the better default

A lot of this terminology is going over my head though, so I guess....sync is best? heh

Unless @amirm has anything to add on the operation of this unit I would use sync mode for USB input and async for SPDIF input.

Although I don't think using async with USB will really degrade anything, but for SPDIF I think jitter will be lower using async.

Amir tested the SPDIF input of the Matrix X-Sabre Pro MQA which has similar async/sync modes here -> https://www.audiosciencereview.com/...-best-audio-dac-in-the-world.8729/post-220500. The J test with async was substantially better.

Michael

 

[AnalogSteph]

Although I don't think using async with USB will really degrade anything,

Well, you should be getting more headroom for intersample overs in sync, as the ASRC is bypassed which otherwise would be responsible for the hard clipping at 0 dBFS that tends to be so typical for ESS-based DACs (unless the manufacturer has explicitly added headroom elsewhere).

A comparison of AKM vs. ESS "sync" might be interesting... hard to keep it comparable though.

 

[MRC01]

Seems like there is some confusion in terminology here. SPDIF is adaptive, meaning the source device delivers the bits according to its own clock and the downstream target device has to adapt itself to the source. No two clocks ever agree exactly, and the target can't tell the source to slow down or speed up, so the target is adapting its own clock rate slightly higher or lower to accommodate the rate at which the data is arriving. Years ago, audio over USB used to work this way too, which was called "adaptive" mode. Later, USB developed a mode called "async" where the target/downstream/receiving device runs off its own clock and asks the upstream/source device for data as it needs it. Think of this as a "pull" instead of "push" protocol. This async mode is more consistent and reliable, usually measures better too especially in jitter.

Here, it sounds like the terms "sync" and "async" are being used in a different context.

 

[mdsimon2]

Well, you should be getting more headroom for intersample overs in sync, as the ASRC is bypassed which otherwise would be responsible for the hard clipping at 0 dBFS that tends to be so typical for ESS-based DACs (unless the manufacturer has explicitly added headroom elsewhere).

A comparison of AKM vs. ESS "sync" might be interesting... hard to keep it comparable though.

Good point.

I would love to see some more data on how different DACs respond to intersample overs and whether clipping is mitigated by the volume control. On the two ESS DACs I've tested (MOTU Ultralite Mk5 and Okto dac8 pro) just knocking the volume down a few dB eliminates any issues with intersample over clipping but I am not sure if this behavior is typical. It also interesting that these DACs do not show typical clipping behavior when fed +3 dB 11.025 kHz tones but rather a +20 dB rise in noise floor, again, not sure if this is typical behavior.

Michael

 

[onlyoneme]

RME ADI-2 with ESS can handle intersample overs +3 dB up to 0 dBFS digital volume level. Typical clipping behavior for higher volume levels.

 

[Mat]

Unless @amirm has anything to add on the operation of this unit I would use async for SPDIF input.

for SPDIF I think jitter will be lower using async.

Isn't it kind of ironic then that async struggles fails to lock onto jittery sources? It sounds good, though, just hard to wrap my head around in practical terms ("If it's jittery use sync, if it's not jittery then use async to get lower jitter")