No I didn't say this - I don't know what the FPGA is doing and won't guess.You've said that the full 4 sec file content is being checked.
Unless you know what FPGA is doing or RME explains, it is just guessing.
I only said that 4s is too short to be on loop so I created 32s in Audacity with copy and paste.
According to what I've seen in the explanations how the test works only part of the file is required to be found for the positive pass.
The only way I could verify this is if I split the 4s into shorter - which is what I wrote above , I did not do.
I guess I could in a few weeks when I get some time. Right now, not a priority but later yes, can check