*Notice: DWA is Data-Weighted Averaging and DEM is Dynamic Element Matching. Although DWA is the most widely used DEM algorithm, these are different thing. I misused the term DWA and I fixed them properly. I apologise for making confusion.
I found this article about new ESS dac. And it starts with "As per Mark Mallinson," which means that it is based on the statement of former Operations Director for ESS Technology.
https://6moons.com/audioreviews2/resonessence/2.html
According to the article, it is Pro and non-Pro version that discriminates ESS dac with/without hump. So Benchmark dac with es9028
pro has no hump, and Khadas tone board with es9038
q2m has hump.
This is Noise vs Input level measurement, not IMD measurement. But according to
audio precision, "The SMPTE IMD measurement includes noise within the passband." So the rise of noise can also effect SMPTE/DIN IMD measurement of Amirm.
And I was right about expecting DEM to be the cause of THD hump of ESS dac.
To simply explain DWA, it is implemented as a circuit that randomly allocates the output signal of delta-sigma modulator to individual 1-bit dac to hide the switching noise and distortion by element mismatch of each dac. But the randomizing algorithm should be designed very carefully in order to maximize its performance.
"This one is a bit complex but a long-standing overlooked potential improvement. It's complex mathematically but relates to 'mapping' the digital signals to analog elements on the chip. The improvement can be seen on lab instrumentation. Both Sabre and Sabre Pro are very very good and better than 1 part in a million.
But what about that bump at -30dB? In the Pro it is now absent to exhibit a predictable noise vs signal level shape. Whilst we have no evidence that this is audible, it
is fixed now."
'Mapping the digital signals to analog element' part is definitely DWA part. I suspect that he tried to explain US 8,984,035 B2 patent because it is about the method of scrambling bit allocation of dac on the output.(but I'm not so sure about this because I'm not an engineer so I can misunderstand the content of the patent.)
https://patentimages.storage.googleapis.com/f0/08/cc/0b71c8764107ee/US8984035.pdf
And furthermore, it seems that the difference between hyperstream and hyperstream II is improved algorithm that controls the noise of dac.
As a result, they have managed to suppress the noise of their dac and it shows well on the graph. This graph is measurement of Dynamic range on y axis, and DC level on x axis. The following picture describes it well.
Source:
https://www.yumpu.com/en/document/read/23182504/noise-shaping-sigma-delta-dacs-ess-technology-inc
So we can predict the relationship between dynamic range and input level or frequency from this graph. And we can also predict that the hump seems to be because of the noise level rising on each end of DC level.
It is a sad thing that usually we can't get this measurement on most dac chip. Only Cirrus logic advertises their effort to deal with this issue.(The blue line on the graph above is cs4398. And they had released a white paper boasting their DEM design on
here) But Texas Instrument and Asahi Kasei also have their own ways to deal with it too.
To conclude, the hump is made by a flaw of hyperstream modulator(although it's still better than old competitors), but it is fixed on PRO lineup.