CFO (Chief Fun Officer)
- Feb 13, 2016
- Seattle Area
Wonder if it would measure better if you tested with a DSD stream so it wouldn’t have to do the conversion? They did say that the conversion from PCM to DSD raises the noise floor of an already noisy FPGA.
As far as I have read, it also upsamaples DSD so it will have to dither anyway.
The noise we are seeing is a combination of analog and digital stages. Unless they can demonstrate it is all from digital stage, in which case their competence is seriously in question with respect to signal processing, I say there is little they can do to impact the noise level of this unit in grand scheme of things. It is short by 30 dB or so to match state-of-the-art DACs. That is a huge, huge gap. Engineers kill for 3 to 6 dB improvement in noise level. 30 dB is an eternity.