Hello everyone,
I'm reviving this thread (after reading though it and not finding my answer...) because my configuration is somewhat similar to the one described by the OP:
- Turntable --> Phono stage --> ADC SPDIF --> MiniDSP open DRC DI -> 2 (parallel) SPDIF Outputs ==>
--> MiniDSP SPDIF Output left --> miniDSP OpenDRC DI left --> CMOS level SPDIF --> 2 Khadas Tone 1 DACs --> 4-Way Power amps
--> MiniDSP SPDIF Output right --> miniDSP OpenDRC DI right --> CMOS level SPDIF --> 2 Khadas Tone 1 DACs --> 4-Way Power amps
Comments:
- The ADC is built into the first openDRC (as clock slave).
- The "parallel" SPDIF Outputs each have their own driver circuit with transformer.
- The Khadas DACs are built into the right and left openDRCs, run in asynchronous mode (according to Khadas) and are fed directly from the miniSHARC boards with the CMOS level SPDIF Signals (i.e. no transformers or level shifters needed).
My question to the experts: Are there any issues with my concept of splitting SPDIF for right and left in the first openDRC and then having separate DSP ... DAC chains with SPDIF connections not synchronised between right and left? If yes, which issues/consequences and how can I handle them?
Thanks and regards,
Winfried
I'm reviving this thread (after reading though it and not finding my answer...) because my configuration is somewhat similar to the one described by the OP:
- Turntable --> Phono stage --> ADC SPDIF --> MiniDSP open DRC DI -> 2 (parallel) SPDIF Outputs ==>
--> MiniDSP SPDIF Output left --> miniDSP OpenDRC DI left --> CMOS level SPDIF --> 2 Khadas Tone 1 DACs --> 4-Way Power amps
--> MiniDSP SPDIF Output right --> miniDSP OpenDRC DI right --> CMOS level SPDIF --> 2 Khadas Tone 1 DACs --> 4-Way Power amps
Comments:
- The ADC is built into the first openDRC (as clock slave).
- The "parallel" SPDIF Outputs each have their own driver circuit with transformer.
- The Khadas DACs are built into the right and left openDRCs, run in asynchronous mode (according to Khadas) and are fed directly from the miniSHARC boards with the CMOS level SPDIF Signals (i.e. no transformers or level shifters needed).
My question to the experts: Are there any issues with my concept of splitting SPDIF for right and left in the first openDRC and then having separate DSP ... DAC chains with SPDIF connections not synchronised between right and left? If yes, which issues/consequences and how can I handle them?
Thanks and regards,
Winfried