But that's the stinginess is cool mentality. Lots of bling-bling, but not paying for it.Parts price has nothing to do with exemplary engineering and performance. You're paying for the designers skill and application, not just the BOM.
... then you also know why.Since there are no (more!) expensive parts inside why does it cost 900$?
Would you pay 1000$ for a box with a copper wire inside ?
Nope, I won't explain.@JohnYang1997 ...can you please explain the following...just curious here:
1. Why use the dual OPA1612 opamps and not the TI OPA1632 or National LME49724 fully differential op-amps for the IV stage or XLR output stages?
2. Your literature says the Altera CPLD is used for clock processing and signal optimization. What parameter is processed/improved with the clocks? Is it jitter? If so, doesn't the ES9038PRO provide enough jitter rejection for your needs, hence the extra processing?
3 CPLD signal optimization. What signal and what optimizations are you doing inside the CPLD?
Thanks!
Guess Topping want to keep at least part of the recipe a secretNope, I won't explain.
Ok, I understand. No worries!Nope, I won't explain.
Hardly surprising, allowing "everybody and his mother" to copy the design is a shot in the foot. Including, but not limited to, China.
If you are passing 44K to 192 K and using ESS built in filter, you don't have to worry about (for so long the DAC designer has not enabled the optional 18 dB gain register to the DAC chip).
However if you are passing 352.8 K and upwards PCM, this 8x interpolation is now disabled.
David - you know everything, create and put your DAC on sale )@JohnYang1997 ...can you please explain the following...just curious here:
1. Why use the dual OPA1612 opamps and not the TI OPA1632 or National LME49724 fully differential op-amps for the IV stage or XLR output stages?
2. Your literature says the Altera CPLD is used for clock processing and signal optimization. What parameter is processed/improved with the clocks? Is it jitter? If so, doesn't the ES9038PRO provide enough jitter rejection for your needs, hence the extra processing?
3 CPLD signal optimization. What signal and what optimizations are you doing inside the CPLD?
Thanks!
1. Why use the dual OPA1612 opamps and not the TI OPA1632 or National LME49724 fully differential op-amps for the IV stage or XLR output stages?
2. Your literature says the Altera CPLD is used for clock processing and signal optimization. What parameter is processed/improved with the clocks? Is it jitter? If so, doesn't the ES9038PRO provide enough jitter rejection for your needs, hence the extra processing?
3 CPLD signal optimization. What signal and what optimizations are you doing inside the CPLD?
Thanks!
John has already pointed out that the CPLD chip is indispensable. Perhaps that has, among other things, what to do with the D90SE offering full MQA decoding on all digital inputs?The use of the CPLD is likely much more difficult to determine without seeing a schematic, much less the programming. It could be doing anything. Though in a product with multiple digital input clocks, clocking functions seem likely. For example, this CPLD + XMOS card uses the CPLD for jitter control on the I2S clock:
Someone also asked about the LT3710. Isn't that a 2nd stage voltage supply? As its right next to an op amp, I would wildly guess that it's providing (maybe a programmable) rail voltage for the analog output.
I did not find a LT3710 on the board.
John has already pointed out that the CPLD chip is indispensable. Perhaps that has, among other things, what to do with the D90SE offering full MQA decoding on all digital inputs?
I did not find a LT3710 on the board. If you mean the small 16-pin chip in front of the outputs, these are just audio switches that replace the relays that are otherwise used. No magic op amps, buffers or amplifiers.