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Topping D90SE Review (Balanced DAC)

Roland68

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Parts price has nothing to do with exemplary engineering and performance. You're paying for the designers skill and application, not just the BOM.
But that's the stinginess is cool mentality. Lots of bling-bling, but not paying for it.
As with these cheap Blender notebooks in electronics stores, lots of bells and whistles and big names, but no quality or durability.
No wonder that so many, including large companies, only use standard solutions instead of doing great development work.
And when you read something like that ...
Since there are no (more!) expensive parts inside why does it cost 900$?
Would you pay 1000$ for a box with a copper wire inside ? :)
... then you also know why.
What would such people say if their boss cut their salary in half because he didn't appreciate your work?

The more I look at the pictures of the D90SE circuit board, the more impressed I am with the circuitry and the new solutions that John and his team have developed.
I've looked in recent years many DAC's and their circuits and the D90SE is the first in which I do not want to access directly to the soldering iron :cool: (and probably would not know what to change ...:confused:)
 
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David_M

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@JohnYang1997 ...can you please explain the following...just curious here:

1. Why use the dual OPA1612 opamps and not the TI OPA1632 or National LME49724 fully differential op-amps for the IV stage or XLR output stages?

2. Your literature says the Altera CPLD is used for clock processing and signal optimization. What parameter is processed/improved with the clocks? Is it jitter? If so, doesn't the ES9038PRO provide enough jitter rejection for your needs, hence the extra processing?

3 CPLD signal optimization. What signal and what optimizations are you doing inside the CPLD?

Thanks!
 

JohnYang1997

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@JohnYang1997 ...can you please explain the following...just curious here:

1. Why use the dual OPA1612 opamps and not the TI OPA1632 or National LME49724 fully differential op-amps for the IV stage or XLR output stages?

2. Your literature says the Altera CPLD is used for clock processing and signal optimization. What parameter is processed/improved with the clocks? Is it jitter? If so, doesn't the ES9038PRO provide enough jitter rejection for your needs, hence the extra processing?

3 CPLD signal optimization. What signal and what optimizations are you doing inside the CPLD?

Thanks!
Nope, I won't explain.
 

respice finem

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Hardly surprising, allowing "everybody and his mother" to copy the design is a shot in the foot. Including, but not limited to, China.
 

nagster

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It's a little disappointing, but JohnYang1997's reaction may be standard as a manufacturer.

Previously he was rampaging.
He was passionate and thorough, with occasional head-on collisions.
That's why his posts were so much I learned.
Due to its sharpness, it often brought out important stories from other engineers as well. I am grateful.
Nostalgic days. Someday again.
 

sq225917

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You're asking him to give away hard found design learnings to anyone who may be reading, no doubt including many other manufacturers staff. Duh.
 

hexxpunk

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If you are passing 44K to 192 K and using ESS built in filter, you don't have to worry about (for so long the DAC designer has not enabled the optional 18 dB gain register to the DAC chip).
However if you are passing 352.8 K and upwards PCM, this 8x interpolation is now disabled.

So if I upsample in HQPlayer to 768khz, then it doesn't matter which of the DAC's 7 filters I have selected, since it bypasses them, correct?
 

Palex

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@JohnYang1997 ...can you please explain the following...just curious here:

1. Why use the dual OPA1612 opamps and not the TI OPA1632 or National LME49724 fully differential op-amps for the IV stage or XLR output stages?

2. Your literature says the Altera CPLD is used for clock processing and signal optimization. What parameter is processed/improved with the clocks? Is it jitter? If so, doesn't the ES9038PRO provide enough jitter rejection for your needs, hence the extra processing?

3 CPLD signal optimization. What signal and what optimizations are you doing inside the CPLD?

Thanks!
David - you know everything, create and put your DAC on sale )
 

lovesegfault

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radix

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1. Why use the dual OPA1612 opamps and not the TI OPA1632 or National LME49724 fully differential op-amps for the IV stage or XLR output stages?

2. Your literature says the Altera CPLD is used for clock processing and signal optimization. What parameter is processed/improved with the clocks? Is it jitter? If so, doesn't the ES9038PRO provide enough jitter rejection for your needs, hence the extra processing?

3 CPLD signal optimization. What signal and what optimizations are you doing inside the CPLD?

Thanks!

Maybe look at the data sheets? The OPA1612 is the lowest noise op amp of all the ones you mentioned. And the lowest THD+N. But there could be many other reasons for choosing one versus another that factor into the overall design of the unit.

The use of the CPLD is likely much more difficult to determine without seeing a schematic, much less the programming. It could be doing anything. Though in a product with multiple digital input clocks, clocking functions seem likely. For example, this CPLD + XMOS card uses the CPLD for jitter control on the I2S clock:

Someone also asked about the LT3710. Isn't that a 2nd stage voltage supply? As its right next to an op amp, I would wildly guess that it's providing (maybe a programmable) rail voltage for the analog output.

While its fun to speculate on parts and such, I think it's great that some manufacturers engage here. Though I think it's most important to engage them on the usability, features, and black-box performance of their gear.
 

NiagaraPete

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Can someone please explain why the need for low impedance balanced inputs/outputs are needed when cable length is normally a couple feet? There shouldn't be any hum or audible noise at that distance?
 

Roland68

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The use of the CPLD is likely much more difficult to determine without seeing a schematic, much less the programming. It could be doing anything. Though in a product with multiple digital input clocks, clocking functions seem likely. For example, this CPLD + XMOS card uses the CPLD for jitter control on the I2S clock:

Someone also asked about the LT3710. Isn't that a 2nd stage voltage supply? As its right next to an op amp, I would wildly guess that it's providing (maybe a programmable) rail voltage for the analog output.
John has already pointed out that the CPLD chip is indispensable. Perhaps that has, among other things, what to do with the D90SE offering full MQA decoding on all digital inputs?
I did not find a LT3710 on the board. If you mean the small 16-pin chip in front of the outputs, these are just audio switches that replace the relays that are otherwise used. No magic op amps, buffers or amplifiers.
 

radix

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I did not find a LT3710 on the board.

I saw in an earlier post in this thread someone asked about at 3710, then said they see it in another DAC too.

I don't have the 90SE (I decided to go with an SHD, as that gives me an all-digital preamp plus phono input plus DSP to analog). But it really looks like a great DAC from the testing on ASR.
 

David_M

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John has already pointed out that the CPLD chip is indispensable. Perhaps that has, among other things, what to do with the D90SE offering full MQA decoding on all digital inputs?
I did not find a LT3710 on the board. If you mean the small 16-pin chip in front of the outputs, these are just audio switches that replace the relays that are otherwise used. No magic op amps, buffers or amplifiers.

MQA decoding is all done via software handled by the ARM-based STM32 microcontroller, I believe. The fixed CPLD is "used for clock processing and signal optimization" as their marketing literature says.
 
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