I have a question about DPLL setting. Manual says:
- When the clock stability of the input signal is good, this value can be reduced, so that the clock performance of the system is better;
- When the clock stability of the input signal is not good, the sound may be interrupted. Increase this value can avoid the sound interruption!
I understand the latter but what does it mean when jitter in input is low, DPLL bandwidth can be reduced and „the clock performance of the system is better“ ? My understanding of DPLL bandwidth is it can be set to:
- low: lock range is small so input jitter has to be low, less of input noise but more of internal noise (vco etc) passed to output
- high: lock range is large so input jitter is OK to be large, more of input noise less of internal noise transferred to output
I understand if input is jittery, it should be high but if it has less jitter and if input (noise) is better than DAC, why making DPLL bandwidth low is a good thing ? Is it impossible for input to be better than DAC (because it is external) ? I am driving SU-9n with Gustard U18 which has a better internal clock, normally I would think since input is better than DAC, I should make DPLL bandwidth high to decrease the internal noise. I dont mean high as MAX setting, but why is it better to reduce it than lets say default ?