While modifying AVCC, I had a closer look at the implementation of the AVCC generation, the I/V-stage and RCA output stage.
Schematic:
I didn't unsolder the caps so I couldn't measure them and I forgot to check the AVCC-buffer negative supply (Gnd would do the job and there's only one decoupling cap, so very likely its +11V / Gnd).
The output stage seems to be a very straightforward I/V stage without de-glitching Cap and without elaborated Common-Mode measures. The ES9039 seems to be well behaved compared to the ES9038 (ESS-hump in IMD- plots) such that these measures are not necessary (the excellent results of Amir's measurements speak for themselves). SMSL choose a potentiometer to do the DC-nulling of the outputs; some other schemes would do this without manual adjustment. It might be, that the potentiometer- solution is the lowest-noise implementation.
The RCA- output amplifier simply subtracts the XLR outputs, applies a gain of ca. 0.5 and does some additional filtering.
The muting is performed by the well known SG3710. This chip seems to have a charge-pump for the internal negative supply such that it can handle +/-11V signal voltage range with just +11V supply. The active-path has an on-resistance of ca. 1 Ohm and the muted-path has ca. 11 Ohms which perfectly makes sense in terms of distortion (low and flat Ron in active position) and chip area (when muted).
AVCC generation:
- LP2985-50 regulator (5.0V)
- resistive voltage divider (R1 / R2 in my schematic); I would have loved to see MELF resistors (metal film) in this position because the tiny 0402 resistors would certainly make some excess current noise in case they are thick-film. Possibly SMSL was considerate and used 0402 thin-film (metal-film) resistors here. This resistive divider brings down the 5V to ca. 3.67V. (In case there is excess current noise, it shows up common-mode at the XLR and at the substractor for the RCA- output such that it will be eliminated to a large extend. So it would be ok. even if the divider consists of thick-film resistors)
- there is some filtering applied. There are two ceramic SMD caps that form an RC-filter with the source-resistance of the divider network.
- the dual OpAmp OPA1612 does the buffering for both channels separately with a capacitor between output and Gnd to bring down the impedance for high frequencies (this is in principal risky (capacitive loading of the OpAmp), but when the cap is large enough, the cap will bring the loop-gain down far enough and the circuit will not oscillate.
EDIT: AVCC buffer U2 might be supplied by +5V / Gnd. I have to check next time I have the unit open.
AVCC modification:
I did not feel comfortable with a AVCC_DAC supply voltage close to the absolute maximum ratings and I looked for a simple modification that is fully reversible.
Since AVCC is generated using a resistive voltage divider, it is straight-forward to simply modify this divider. I decided not to change one of the tiny 0402 resistors, but instead solder a resistor in parallel to R2 (the resistor that goes to Gnd). Soldering a 0603 resistor on top of one of the two filter caps (that are in parallel to R2) is a very conveniant and safe way (see photo).
A parallel resistor with 22k will bring AVCC down to approximately 3.31V. It would be nice to use a metal-film (thinfilm) resistor - see above).
In case you decide to do this modification, you can check the result by measuring AVCC at the outputs of the OPA1612. There is a footprint where no SMD component is fitted (see photo). AVCC should be ca. 3.31V after the modification.
(I would recommend to check AVCC before and after the modification; SMSL might have changed the resistor values during production such that it needs a different value for the parallel resistor).
EDIT: I would also check the offset voltage on the XLR outputs. The "+" and "-" are a bit different and both should be within ca. +/-1 ... 2mV compared to Gnd. If this is not the case you can adjust the small potentiometers located between DAC-chip and OpAmps. For both of my units no re-adjustment was necessary.
The RCA output is close to 0mV anyway because it subtracts "+" and "-" of the XLR.
Output level:
The output current of the DAC scales with AVCC such that a reduction of AVCC will reduce the output voltage by the same ratio. 20*log(3.309/3.665) = -089dB
Noise:
I would expect that the noise does not scale with AVCC. I did measure something like 0.2 dB less noise with AVCC = 3.31V, but in case this is real, it's basically "academic"
Distortion:
Within my measuring capabilities I did not observe increased distortion with AVCC = 3.31V compared to 3.67V. Measurement condition was 1 kHz sinewave at 0dBFS generated with REW. I did measure with a passive notch filter and an Audio-Precision Portable-One as analog frontend for the (not so nice) USB audio-interface. A second instance of the REW with Real-Time-Analyzer was used to observe the spectrum. With "coherent averaging" (a method that suppresses non-harmonic noise) I can measure down to ca. -140dBc.
(I verfied the distortion measurement capability by adding -120dBFS of k2 and k3 (in REW); these lines then rose by almost 20dB).
Conclusion AVCC modification:
Bringing down AVCC to the nominal value of 3.3V (+/-5% according to the datasheet) will lower the output level by ca. 0.9dB. Since noise does not (or only little) scale with AVCC, SINAD will be worse by ca. 0.7 ... 0.9dB. This has no practical relevance to my humble opinion, but it would surely affect the position of the D-6s in the "Best in SINAD" plot.
As already mentioned, I do assume ESS has designed the ES9039 for 24/7 and for customers expecting a lifetime >10 years. It is therefore very possible that the D-6s "as produced" will work as expected for many, many years. Being familiar with CMOS IC design and product qualification, I just felt I should trade 1dB in SINAD for a good conscience
PS: I'm absolutely happy with this DAC. It looks nice, the features are just perfect and -last not least - it has a stellar performance.
www.audiophonics.fr
