is this a valid way of synchronizing two USB DACs?

[MC_RME]

If word is implemented correctly the converters will run sample aligned to the rising word clock edge. Jitter is always sub-sample, so a PLL does not prevent one from getting the right 'starting point'.

 

[MCH]

If word is implemented correctly the converters will run sample aligned to the rising word clock edge. Jitter is always sub-sample, so a PLL does not prevent one from getting the right 'starting point'.

Thanks, I had understood the opposite from the manual's text. Now it is clear.