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Building a usb headphone amp R2R

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#1
Hi,
I’m looking to build a usb pcm-r2r ladder headphone amp. 32bit/192kHz linear pcm input (OSX provides transcoding). My background university degree in parallel and distributed systems, along with embedded formal systems, GPU Astro image processing deconvolution using DFT, and I for the last 6 months been involved in quantum computing in a bank (using QFFT). I almost bought a TacT Millenium 20 odd years ago..
However hardware itself I’m a beginner..

My initial thinking design used;
LT3045 (six in parallel) providing 2.5A at 3.3v fed by toroidal with choke full wave rectifier plus a ground circuit rectifier etc
Xmos xu208 usb to i2s (no spdif)
NVE IL715 to decouple i2s and i2c
Artix a7 fpga ddr for fifo and reclocking the i2s stream
CPLD to manage each channel resistor ladder output as a 24bit ladder
Output from the ladder via an active low pass Sallen-Key Bessel filter with RC final low pass filter to ensure top end. The active filter will use TL074 op amps (better characteristics for PWM) plus DC detect and short circuit protection.
AD 9516 as a masterclock for all devices

As I have researched more I now understand a little more about the odd order harmonics and the relationship to square waves; plus the general idea to minimise the them using small transitions, either 100% or 0% duty, centre sample clocking, plus pre-processing.
I understand the need for doubling tolerance for each ladder bit added and the must low noise power and grounds.

I’ve also see a number of implementations including Soekris’s dam1021-12 1% version that seems decent, reading the review here I note that the DIY DAC used a HK TL3045-based power regulator - I would point out that the basic version only comes with two 3045s, a max of 1A but the noise level for the regulator increases over 60% duty. It may explain some of the mains noise.
The Soekris 1% still remains an option rather than building.. I’ve dissected the board picture and it appears to use 4 banks of resistors in a 7bit configuration with each bank using a 74LVC595A programmed by the fpga to set the bits for the ladder and synchronise the pulse against the shared pwm clock. The resistors look like Vishay 0.001% MR10s.
It looks like it’s double banked per channel to double current delivery into the final capacitor before coming out unbalanced, the balanced drivers then take the output. I’d still add an active and passive low pass filter - one didn’t jump out from the image.

I have a couple of questions;

Q1) has anyone used a fgpa based curve fitting when upscaling from sample rate to 8x pwm switching rate?
The likes of Fermilab and CERN fit curves for particle tracks from the detectors using FPGAs with minimal resources. The curve fitting can be used to fill in the upsampled pwm values. Idea being to use the curve to reduce sample transposition sizes reducing the odd harmonics.
A second fgpa could be added as a pipeline upscaler if the main fpga didn’t have enough logic elements.

Q2) anyone taken each bank output, splitting with one side being inverted through a high pass filter, before being summed bank in to the ladder output? The summation cancels the harmonics for the bank output further up the frequency range. Each bank’s are then reducted?
I’m wondering if this technique would reduce the tolerance required for ladder resistors as the number of bits increase.

Any thoughts/wisdom?
 
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#3
One thing looking at what I’ve written - changing the TL074 to a OPA165x is that may be better for the active low pass filter, although I would check the maximum slew rate based on say a 20KHz tone (transition slope wouldn’t be vertical) with a full transition from 0 to 3.3V.

TL074 slew rate is 13V/uS vs OPA at 10V/uS.

The OPA slays the TL at THD (TL is 0.003%) and noise at 1kHz (TL is 18nV vs 4.5).
 

DonH56

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#4
Many, but not time to reply right now... Here are some random quick thoughts.

This is pretty far from an implementation that achieves SOTA performance, and using an FPGA or CPLD for switches is going to introduce a lot of noise and distortion. Resistor matching and controlling local and global gradients is somewhat an art -- the science is pretty well-understood but non-trivial. You'll want to use a segmented design to make matching more realizable and reduce average switching glitches (e.g. splitting the 4 MSBs into unary segments reduces matching from ~1/65,536 to ~1/4,096 for a 16-bit converter, still pretty stringent). Matching and layout is a huge effort in a discrete design.

Using a S-K architecture might work but Bessel, while perhaps better preserving time-domain response, will have too slow a roll-off in a reasonable implementation to provide effective anti-image filtering. I am not sure why the heavy power supply nor some of the component choices -- if I was building my own I'd probably build the supply in a separate box.

Upsampling is a big topic in filter design. The algorithms I have seen and used are generally more complex than linear interpolation (think sinc functions and such). I am not sure the correlation to odd harmonics; that depends on many factors in the design (and not just the filter architecture). Splitting and summing multiple banks means a pretty deep dive into matching and controlling transitions in time and amplitude; realizing low distortion is very challenging. I am not up on the latest audio op-amps but the TL074 is a pretty old choice. Fairly low noise and JFET inputs with decent gain-bandwidth but I would look for a lower-noise, wider-bandwidth op-amp these days.

I have some old Mathcad programs that do a nice job of comparing trades among segmenting (unary/binary bits) and showing what happens as you add random and global segment variations (like bows due to voltage across the switches or thermal gradients) but am not sure it still runs. My Matlab versions were lost years ago; keep thinking I should transfer my programs over (bought Matlab for myself again a few years ago, just never had time to do much with it -- too busy with Work and Life).

There are many artricles on the web, and many experts on ASR far better than I on audio converters (my experience is mainly RF/mW), but here are a few threads you might check out for basic introductory material -- there is a bit on segmentation and jitter, among other things:

https://www.audiosciencereview.com/forum/index.php?threads/digital-audio-sampling-101.1919/
https://www.audiosciencereview.com/...ital-audio-converters-dacs-fundamentals.1927/
https://www.audiosciencereview.com/...igma-delta-digital-audio-converters-dac.1928/
https://www.audiosciencereview.com/forum/index.php?threads/digital-audio-jitter-fundamentals.1922/
https://www.audiosciencereview.com/...igital-audio-jitter-fundamentals-part-2.1926/

Amir and others have also written a number of technical articles in the Audio Reference LIbrary sub-forum.

It's a big project, maybe you would prefer a nice game of chess? :)

HTH - Don
 
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#5
It's a big project, maybe you would prefer a nice game of chess? :)

HTH - Don
Ok will have a read - thank you for taking the time to respond.

Low pass sinc, I assume the part of the idea is to compensate for constant ladder pwm characteristics by applying the filter to the input. Will have a look into it.

it should be possible to connect the input and output to an external computer and let Neural network (probably a CNN or a tensor ODE variant) to define the parameter values required in the filtering to correct the frequency responses of that manufactured R2R ladder unit..

Most of the system would be modular, so I can start with bare bones and then go from there.

If computers can beat us at Chess, Go and Startcraft.. better make them earn their keep!
 

DonH56

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#6
The sinc^n filter is on the output to suppress the images generated by the DAC. By oversampling you can get away with a low-order filter.
 
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I’d started reading these in relation;
https://www.analog.com/media/cn/training-seminars/tutorials/MT-017.pdf
http://www.ti.com/lit/an/sbaa230/sbaa230.pdf
https://www.maximintegrated.com/en/design/technical-documents/app-notes/3/3853.html

for Astro work, the images are seen as 2D (separable into two 1D) signals - hence using phase correlation, Fft filters, saturation estimation (z-phase correlation). All with low SNR images (noise from cooled CCD sensors, scope aberrations, atmosphere, Satellites, planes, all made more fun as it changes with wavelengths of light too). Ringing artifacts that you see from overshooting is more visable around stars for example. All very related.
 
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DonH56

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#8
Fred Irons and Dan Asta (prof at MIT and one of his students; I worked some with Fred, a lot with Dan, ages ago) wrote some good papers on phase-plane compensation and related techniques for dynamic compensation many years ago. You may need more than static compensation, and note need some sort of trim circuit/algorithm with sub-lsb resolution in the HW side of the DAC.

I worked somewhat with imagers, mostly CCD-based, many years ago. My job was primarily the ADC and clock driver design. We also implemented sampled-analog filters (continuous amplitude, discrete time) using CCDs. Fun stuff.
 
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#9
Let me break out Jupiter notebook octave.

I can then simulate it.

python using scipy, pySPICE (ngspice) would work. Seems ngspice has a Monte Carlo simulation which could work well for R2R tolerances.
 
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#10
Ok, I've costed up the options.. Soekris' offering (for the hardware) is good with the OEM - and the new board with sign-magnatude certainly looks good.

I've modelled some of the filters in Octave - I see that Soekris uses a zero insertion upsample which is a neat touch with 67bit adder and 32bit coefficients. Octave is single threaded, dog slow even with vectorisation but works.

Also has helped finish an idea that has been cooking for the astro stuff! Noise reduction idea for the astro stuff using the convolution of the earths atmosphere to remove local noise from the CDD image prior to deconvolution.

Just trying out ideas, for example:
Screenshot 2019-12-29 at 23.10.45.png
 

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