KSTR
Major Contributor
- Thread Starter
- #21
A few days ago RME has released a beta version of the upcoming firmware revision which fixes the problem, and I could confirm that by repeating the initial measurement in post #1.
Now the staircase waveform is reproduced faithfully, with full symmetry:
As an additional check of digital signal integrity I also recorded the RME's response with the local DAC level setting at -15dBr, which means the signal must be rendered with dithering to obtain mean values that are not LSB multiples anymore. The block averaging also reduces the dither noise and this is what we get:
Even though we're talking sub-LSB levels here (-15dBr digital DAC gain means one input bit is ~18% of an output LSB), those steps are still visible and have the correct relationships. The first "-1" value (cursor) looks a bit weak and the DC offset for "0" looks to be slightly negative, but now we are approaching ADC limits and this little error, in case it really came from the DAC and pre-processing, would be truly academic anyway.
From this results I would conclude that the preprocessing in the RME Adi2- Pro is 100% flawless now.
The internal resolution, needed for proper digital level reduction and re-dithering for the actual DAC chip input also showed to be fully adequate (and probably has always been), though I'm not clear about the significance of this measurement.
Big thanks to RME and Mathias for taking action to remove this little processing glitch.
Now the staircase waveform is reproduced faithfully, with full symmetry:
As an additional check of digital signal integrity I also recorded the RME's response with the local DAC level setting at -15dBr, which means the signal must be rendered with dithering to obtain mean values that are not LSB multiples anymore. The block averaging also reduces the dither noise and this is what we get:
Even though we're talking sub-LSB levels here (-15dBr digital DAC gain means one input bit is ~18% of an output LSB), those steps are still visible and have the correct relationships. The first "-1" value (cursor) looks a bit weak and the DC offset for "0" looks to be slightly negative, but now we are approaching ADC limits and this little error, in case it really came from the DAC and pre-processing, would be truly academic anyway.
From this results I would conclude that the preprocessing in the RME Adi2- Pro is 100% flawless now.
The internal resolution, needed for proper digital level reduction and re-dithering for the actual DAC chip input also showed to be fully adequate (and probably has always been), though I'm not clear about the significance of this measurement.
Big thanks to RME and Mathias for taking action to remove this little processing glitch.