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ESS THD ‘Hump’ Investigation

IVX

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Fortunately, XMOS is quite normal Si company like Ti/Ad/St who design their stuff and next actively promote that in a public domain, so I hope it is not a big deal to build an interface on XMOS ICs. Try to get any appnotes from cmedia or ess and others tiny taiwanese companies, if you seriously looking for a headache )) My project using CM6642 + ES9038Q2M + bridged_AD8397 on the PCB 20x47mm. It is kinda USB dongle headphone amp with balanced outputs only. So I spent probably a few months to get app-info for CM6642, it is crazy stupid police to design a chip and hide it from customers! And now seems the same things I need to do with ES9038Q2M ))
 

IVX

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oh, this one I have, of course, anyone googled for "es9038q2m" got it ;) I'm talking about appnotes, normal one like Ti makes and other serious companies. es9038q2m.pdf is too short it is just a list of registers where is not all is clear to me. Actually, for ak4490 I used only main datasheet to get proto working, even didn't check for appnotes. Probably my es9038q2m is dead due to RT1 pin was float during first turn On. I have one more chip but it so painful to replace the old one, OMG!
PS: sorry for two pics, no idea why it happened and how to delete one..
WeChat Image_20190304133329.jpg
 
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IVX

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Guys, I had mistake around 'b' vs 'd' i.e. Binary vs Decimal numbers, which mixed everywhere in that ugly datasheet )) Now I see the AC wave on the DAC's outputs, however DC levels on it not right. According to datasheet 1.65VDC, I have 2.27/1.24 and 2.36/2.78 and of course, my output opamps are saturated at 5V and 0V :(
 

Veri

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Maybe allo knows the magic about ESS THD compensation control? from their product page: https://www.allo.com/sparky/katana.html

Each board is hand-trimmed (individually) for DC offset (when board is warm to simulate conditions of a board that been running for at least 45 minutes), and then programmed for THD+N compensation.
 

andreasmaaan

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Maybe allo knows the magic about ESS THD compensation control? from their product page: https://www.allo.com/sparky/katana.html

Each board is hand-trimmed (individually) for DC offset (when board is warm to simulate conditions of a board that been running for at least 45 minutes), and then programmed for THD+N compensation.
Hand-trimmed!?
 

IVX

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Hi there, I just tried THD_comp with my not really finished proto.
1) ES9038Q2M.pdf has a mistake, and real default state of reg#13 = 0x40 i.e. THD_comp is Off, to turn it On need to send zero to the reg#13.
2) Reg#25 is MSB, reg#24 is LSB for 3rd harmonic compensation, bit#7 of reg#25 seems the sign or phase 0/180 for harmonic.
3) When I a bit compensate 3rd harmonic at -10db level, I getting double THD for -3db level yet, so that's fine for very particular level ONLY, at least in my case. My proto needs to be polished next couple weeks to get THD+N < .0005%@ real headphone load, so far I see 10x worse, however, S/N is already ok and looks <-120db(A). I gonna repeat THD_comp experiments when my proto will be ok for THD+N.
 

IVX

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1) according to ES9038Q2M.pdf there are only 1 coefficient for 2nd and 1 for 3rd harmonic, so I see no way to implement your idea
2) I don't know how to avoid the generation of new THD if THD_comp coefficient will be dynamically changed on the fly. It is time domain..
 
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May I ask how you calculated coefficient value? or Based on testing? Thanks.
Of course it is based on testing.
In fact, the optimal value of this set of coefficients depends on the specific PCB layout and parasitic parameters of the external components.
In addition, if the ESS DAC output noise floor is not low enough, the harmonic components will be overwhelmed by the noise floor, and adjusting the THD COMP coefficient will have no effect.
 
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I'm looking for some solution for khadas tone board hump, if update a firmware can solve this issue, that will be great.
 

Veri

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I'm looking for some solution for khadas tone board hump, if update a firmware can solve this issue, that will be great.
Since this is a very complex problem with so far no straightforward solution, this will not be fixed by software. If there is any fix, it will be hardware from what I see..
 
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I post this in March audio dac1 one thread but belongs here. I ran a level sweep versus THD, i.e. excluding the noise, and the problem appears plainly there:



It is remarkable in how they give up 20 dB of distortion the moment levels get beyond -40 dB. It seems like a design problem but how would a company like ESS let this get out this way???
Would it be too much to ask to run this test on a DAC that does not exhibit this issue for the purpose of comparison?
 

IVX

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I did some tests with different clocks, and noticed THD improvement from noname 100MHz 3.3V OSC to SiTime SiT8209 and further with 50MHz Epsol crystal + internal DAC's OSC. The biggest improvement I got when replaced 100MHz OSC to SiT8209, don't remember exactly because I made many others modifications as well to improve THD, I think at least from .001% to .0006% step down only due to SiT8209. And Epcos standard crystal+internal 9038q2m oscillator reduces THD up to .00045%(or .00025% after THD_COMP tweaking) on my proto-board, which is highly optimized for a min size(USB dongle, I posted the pic here). Of course, I glad to get such a perfect clock for 1/30 of SiT8209 cost but 50MHz simply don't catch Fs=192, only <=96, so I need to use 100MHz crystal anyway. Unfortunately, 100MHz Xtals available in 5032 or bigger case.. It seems 9038q2m datasheet has mistake regarding 100MHz as max Xi, it rather min or the only single valid frequency, at least for SPDIF at 192.
 
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