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Can't understand something simple

Merida

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I read the following sentence in this The Scientist and Engineer's Guide to Digital Signal Processing By Steven W. Smith which talks about ADC & DACs.

"For example, suppose that the ones and zeros are represented by 5 volts and 0 volts, respectively. If 80% of the bits in the data stream are ones, and 20% are zeros, the output of the low-pass filter will be 4 volts. "

I tried making sense of it, but i can't. Lets say 5 is represented in binary form as 101 and 0 as 000. how does a LPF covert the output into 4 volts or 100?
 
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Merida

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alright, so if it were a stream of bits represented in a 12 bit format,

00000000010100000000000.

This in terms of pulses will be two pulses while the rest are all 0s. Therefore using a LPF will get rid of trailing pulse, thus ending up with

00000000010000000000000

and hence 4 volts. Is that right ?
 

Don Hills

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That article is about the way a single-bit DAC works. It is the principle behind modern Sigma-Delta DACs, and the way SACD / DSD data streams are D-A converted.
In your example, if the DAC were fed the PCM value 4 (100), it would generate a stream of 1s and 0s which would average out to 4 volts. Because the input PCM values can be 0,1,2,3,4 or 5, the output 0/1 bitstream to the filter must have at least 5 bits for each input value, so that the average of the bits works out to the desired voltage after the filter.

bravomail said it's like PWM, but it is actually closer to PDM (Pulse Density Modulation).
https://en.wikipedia.org/wiki/Pulse-density_modulation

Or, approximately, the way a DSD DAC works:
https://en.wikipedia.org/wiki/Direct_Stream_Digital
 

DonH56

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Given a 1 = 5 V and a 0 = 0 V you might have these bit streams:

100% 1's = 11111111111111111111...
_80% 1's = 11111111001111111100...
_50% 1's = 11111000001111100000...
_10% 1's = 10000000001000000000...
__0% 1's = 00000000000000000000...


When you integrate (filter) the output the all-1's signal is a constant 5 V. The 80% 1's signal is slightly lower since there are a few 0's thrown in and so with the right pattern and integration you'll get 4 V output (0.8 * 5 V = 4 V). At 50% density of 1's, 2.5 V; down to 0.5 V at 10%, and 0 V for no 1's in the bitstream. But note that pattern (run) length matters (among many other things).

For example, these two streams both exhibit 50% density over the long term but provide very different output signals:

50% version 1 = 11111000001111100000... (output frequency = fs/10)
50% version 2 = 10101010101010101010... (output frequency = fs/2)


This is a simple (and simplistic) way of looking at the output of a 1-bit DAC without fancy filtering and ignoring the distribution of the 1's and 0's in the bit stream, sampling rate, etc. Different patterns applied to different filters with the same long-term bit density may have slightly different outputs.

HTH - Don
 
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Merida

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Given a 1 = 5 V and a 0 = 0 V you might have these bit streams:

100% 1's = 11111111111111111111...
_80% 1's = 11111111001111111100...
_50% 1's = 11111000001111100000...
_10% 1's = 10000000001000000000...
__0% 1's = 00000000000000000000...


When you integrate (filter) the output the all-1's signal is a constant 5 V. The 80% 1's signal is slightly lower since there are a few 0's thrown in and so with the right pattern and integration you'll get 4 V output (0.8 * 5 V = 4 V). At 50% density of 1's, 2.5 V; down to 0.5 V at 10%, and 0 V for no 1's in the bitstream. Pattern length matters (among many other things).

For example, these two streams both exhibit 50% density over the long term but provide very different output signals:

50% version 1 = 11111000001111100000...
50% version 2 = 10101010101010101010...


This is a simple (and simplistic) way of looking at the output of a 1-bit DAC without fancy filtering and ignoring the distribution of the 1's and 0's in the bit stream, sampling rate, etc. Different patterns applied to different filters with the same long-term bit density may have slightly different outputs.

HTH - Don

Don,

that was very helpful. thank you. :))
 
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