Topping D70s MQA Review (DAC)

[GTAXL]

Wow, what happened to the S/PDIF jitter? The D90 had much better jitter yet they are using the same AK4118. Looks like they dropped the ball on implementation here.. Needless to say, for roughly the same price I'd go with the D90.

 

[GTAXL]

Is it a reclocker Or a resampler? I am not familiar with ESS Dacs, if it is in fact the right terminology, or the terminology they use, does someone knows what it means in this application?

From the ESS datasheets I've seen, they aren't using an SRC. The DAC chip, such as ES9068AS has a built in S/PDIF receiver and analog PLL. This is why the jitter performance from it was excellent. I don't think it did any re-sampling.

 

[PeteL]

Wow, what happened to the S/PDIF jitter? The D90 had much better jitter yet they are using the same AK4118. Looks like they dropped the ball on implementation here.. Needless to say, for roughly the same price I'd go with the D90.

maybe not the same crystals tough, the D90 is after all the flagship products and this is the kind of part where a very small improvement bump the price exponentially. Yes "femto clock" may be a marketing hype, but it does show on measurments. Now, the MQA version of the D90 is 800$, to me it's not "roughly the same price" It's significant.

 

[JohnYang1997]

From the ESS datasheets I've seen, they aren't using an SRC. The DAC chip, such as ES9068AS has a built in S/PDIF receiver and analog PLL. This is why the jitter performance from it was excellent. I don't think it did any re-sampling.

Everyone knows that ESS has built in high performance ASRC. The PLL you are mentioning is extra clock circuit for convenience. You can bypass it and still run 44.1k and 48k with single oscillator.

 

[Veri]

From the ESS datasheets I've seen, they aren't using an SRC. The DAC chip, such as ES9068AS has a built in S/PDIF receiver and analog PLL. This is why the jitter performance from it was excellent. I don't think it did any re-sampling.

ASRC will be on unless the implementation explicitly prohibits it. Only a few DACs leave that that up to the user (Matrix X-Sabre, Allo Revolution, ...)

 

[PeteL]

Everyone knows that ESS has built in high performance ASRC. The PLL you are mentioning is extra clock circuit for convenience. You can bypass it and still run 44.1k and 48k with single oscillator.

Yes I later read this. I still don't know if "resampling" is the proper name tough but I get what Amir could have meant. But after all, doesn't AKM upsample too, for filtering duties? I do get why you would want to upsample to turn spdif into asyncronous, some other small dac manufacturers do it trough fpga as well.

 

[JohnYang1997]

Yes I later read this. I still don't know if "resampling" is the proper name tough but I get what Amir could have meant. But after all, doesn't AKM upsample too, for filtering duties? I do get why you would want to upsample to turn spdif into asyncronous, some other small dac manufacturers do it trough fpga as well.

Resampling is strictly correct. And the ASRC is meant to reduce jitter and simplify implementation.

 

[Veri]

But after all, doesn't AKM upsample too, for filtering duties?

I believe ASRC (Asynchronous Sample Rate Conversion) happens at the input, so it manipulates the data before feeding it to the DAC, whereas the DAC oversampling filter happens in the DAC stage, so after the input. The standard OS filtering won't help external jitter.

 

[PeteL]

I believe ASRC (Asynchronous Sample Rate Conversion) happens at the input, so it manipulates the data before feeding it to the DAC, whereas the DAC oversampling filter happens in the DAC stage, so after the input. The standard OS filtering won't help external jitter.

You are both correct and I do know what ASRC means, an how it's used to reduce jitter. I just personally use upsampling or oversampling, to me resampling means something else, maybe my french, not a big deal anyway, when I first asked the question I did not know ESS had a ASRC provision and wanted clarification. I since read the datasheet. strictly upsampling wouldn't help jitter because at the filtering stage the you are not resynchronizing anything, to turn a real time protocol into asynchronous, you need a buffering stage.

 

[GTAXL]

maybe not the same crystals tough, the D90 is after all the flagship products and this is the kind of part where a very small improvement bump the price exponentially. Yes "femto clock" may be a marketing hype, but it does show on measurments. Now, the MQA version of the D90 is 800$, to me it's not "roughly the same price" It's significant.

Wasn't comparing the MQA, could care less about MQA, just was comparing to the D90 and general performance. I thought when using S/PDIF the DAC will use the clock from the source, not the onboard clock, I thought it got the clock from the AK4118's PLL. I could be wrong and the AK4118 is "syncing" the onboard clock with the source s/pdif clock. Someone correct me as I'm not too familiar with the technical aspects of this. Just that they both used the same receiver chip yet have much different jitter results.

Everyone knows that ESS has built in high performance ASRC. The PLL you are mentioning is extra clock circuit for convenience. You can bypass it and still run 44.1k and 48k with single oscillator.

Ok, well I didn't see it listed anywhere in the datasheet I'm looking at, just that it did mention PLL and S/PDIF receiver built in, which I attributed to why the jitter performance for S/PDIF would be excellent compared to using something like the AK4118.

 

[PeteL]

I thought it got the clock from the AK4118's PLL. I could be wrong and the AK4118 is "syncing" the onboard clock with the source s/pdif clock. Someone correct me as I'm not too familiar with the technical aspects of this. Just that they both used the same receiver chip yet have much different jitter results.

It could be all three. It can use the internal PLL but the performance is better with an external master clock. In most implementations, the 4118 try to reclock the samples using the master clock, but since it's a real time thing, if the drift become significant, it'll revert to the incoming spdif clock.

 

[PeteL]

Ok, well I didn't see it listed anywhere in the datasheet I'm looking at, just that it did mention PLL and S/PDIF receiver built in, which I attributed to why the jitter performance for S/PDIF would be excellent compared to using something like the AK4118.

I think they are talking about the es9038 pro. It's quite clearly mentioned. I wouldn't know about the other ess chips.

 

[GTAXL]

I think they are tasking about the es9038 pro. It's quite clearly mentioned. I wouldn't know about the other ess chips.

I was talking about the ES9068AS which is what is used in the Gustard x16 which has excellent S/PDIF jitter.

It could be all three. It can use the internal PLL but the performance is better with an external master clock. In most implementations, the 4118 try to reclock the samples using the master clock, but since it's a real time thing, if the drift become significant, it'll revert to the incoming spdif clock.

Thanks for the clarification. I would think using the incoming spdif clock would be better as it's the one with the correct timing for the samples? So does the AK4118 "sync" the onboard clock to the spdif clock, or the onboard clock operates independent of the spdif clock and the input is resampled to match the onboard clock instead of spdif clock? That's what I'm confused on. In the case of the Gustard x16, would it of been using the onboard clock or the spdif clock, if the spdif receiver is built into the DAC chip and has it's internal PLL? I'd assume it'd be using the spdif clock..

 

[YSC]

Anyone can teach something on how will jitter be listened as artefact? I always see graphs of lots of spikes in jitter but owned those dacs and I can’t hear a hint of distortion

 

[PeteL]

I was talking about the ES9068AS which is what is used in the Gustard x16 which has excellent S/PDIF jitter.


Thanks for the clarification. I would think using the incoming spdif clock would be better as it's the one with the correct timing for the samples? So does the AK4118 "sync" the onboard clock to the spdif clock, or the onboard clock operates independent of the spdif clock and the input is resampled to match the onboard clock instead of spdif clock? That's what I'm confused on. In the case of the Gustard x16, would it of been using the onboard clock or the spdif clock, if the spdif receiver is built into the DAC chip and has it's internal PLL? I'd assume it'd be using the spdif clock..

Well the correct timing for the sample is the most exact sample rate. The spdif clock, can only be as accurate as the clock of the source device. When designing a DAC you would prefer to rely on the precision you know. Plus, this clocking signal traveled, it is as with any signal not immune to interference, to some noise. If you add noise to a square wave, it's not as square anymore. In the case of an toslink, interference is not an issue, but the physical limitations of the optical signal impose a treshold on the accuracy, think of it as a square wave drawn with a fatter pen.

 

[GTAXL]

Anyone can teach something on how will jitter be listened as artefact? I always see graphs of lots of spikes in jitter but owned those dacs and I can’t hear a hint of distortion

As long as it's under -120dB it's really a non-issue and can't be heard. I use the Topping D90 over AES/EBU, no issues, sounds excellent. No delays, ticks, or anything. My source clock in the chain is professional audio equipment, the Lynx Hilo. Why do I use AES/EBU over USB? Well that's a debate for another time and another forum, but I've always had issues with USB audio, even XMOS based devices on my particular workstation. Plus I plan on connecting very high end equipment such as PM2, Lavry Gold, etc. that are AES/EBU only.

The reason jitter was brought up so much here, is cuz I do believe Topping dropped the ball on the D70S, when the D90 does better..

 

[Francis Vaughan]

The jitter magic in the ESS DACs is in the manner in which they do clock detection and how that detection insulates the phase locked loop from jitter in the incoming data stream. They perform a high speed sampling of incoming data and determine moving averages of the inter-edge period. They do this as part of the data reading process from the Manchester encoded data. This gives them a very stable and controlled metric of the actual data rate which is used to control a DPLL.
This is a neat trick, and very different to using an ASRC for jitter isolation.

 

[YSC]

As long as it's under -120dB it's really a non-issue and can't be heard. I use the Topping D90 over AES/EBU, no issues, sounds excellent. No delays, ticks, or anything. My source clock in the chain is professional audio equipment, the Lynx Hilo. Why do I use AES/EBU over USB? Well that's a debate for another time and another forum, but I've always had issues with USB audio, even XMOS based devices on my particular workstation. Plus I plan on connecting very high end equipment such as PM2, Lavry Gold, etc. that are AES/EBU only.

The reason jitter was brought up so much here, is cuz I do believe Topping dropped the ball on the D70S, when the D90 does better..

I am using a holoaudio spring 2, the jitter is in ~110db range and in higher frequencies it’s approaching 100db and can’t here a thing, just wonders what should it appear as if it was heard

 

[Matias]

As an owner of a Makua (Tambaqui inside a preamp) I got to say this is very impressive.

Below the "elite" multitone champs in increasing price.

Gustard X16 (500 usd)

Topping D70s (650 usd)

Okto dac8 stereo (1,240 usd)

Mola Mola Tambaqui (11,500 usd)

 

[Atanasi]

Anyone can teach something on how will jitter be listened as artefact?

There are some simulations: https://archimago.blogspot.com/2018/08/demo-musings-lets-listen-to-some-jitter.html