yes and no.
the other chips are without dpll function , so combine them you need a outside clock signal and dpll to produce a single clock signal to all chips and path , so they are all synced in digital signal.
combine them is like linear time invarant system ,
you add the signal and noise , because the noise is white and adding them will not double the level , you can have " gain" to increase SNR.
it is a common technique in wireless communication, most important one in 3G system, in which Qualcomm invented RAKE receiver which can combine signals from different path and base station. and many many other like HARQ later on.
but for cs43198 it has own DPLL function on each chip which means it may differ for each chip in clock syncing , basically there is an independent clock source for each chip,if these chip's dpll behave differently. and because dpll process needs time to adjust frequency dynamically and lock phase , and it is like a negative feedback process, it breaks the linear time invaraint rules of the singal and system textbook . so adding them adds up the timing errors.
I read from some tearing up d30pro thread , they say the 4 chips are fro L+ L- R+ R - in xlr , so the combine phase is in the amp.
I suggest to test the RCA out, which only use one chip for L and one for R channel, if it is better, my guess is verified!!!
