solderdude
Grand Contributor
PLL's are actually used to lock on incoming frequencies and make the oscillator match that (in frequency and phase). The clock in most cases is a divided master clock and thu smultiply the incoming SPDIF clock and do this phase locked.
The reason for using that is to prevent buffer over- and under-run and so different frequencies (44.1 and 48kHz multiples) can be synced to different internal clocks.
I have explained the clock synchronizing thing above.
The 3 PLLs will also have jitter and depending on the kind of jitter certain amounts of jitter may well be 'averaged' a bit.
As I have explained before. The jitter of a DAC is not caused by the master clock but by other circuits and any decent DAC with jitter reduction circuits (on the input where jitter is a potential issue) is already below thresholds.
It is similar to believing SINAD 123 is better than SINAD 120. From a measurement p.o.v. it is but from a practical (audible) standpoint it is not.
The reason for using that is to prevent buffer over- and under-run and so different frequencies (44.1 and 48kHz multiples) can be synced to different internal clocks.
I have explained the clock synchronizing thing above.
The 3 PLLs will also have jitter and depending on the kind of jitter certain amounts of jitter may well be 'averaged' a bit.
As I have explained before. The jitter of a DAC is not caused by the master clock but by other circuits and any decent DAC with jitter reduction circuits (on the input where jitter is a potential issue) is already below thresholds.
It is similar to believing SINAD 123 is better than SINAD 120. From a measurement p.o.v. it is but from a practical (audible) standpoint it is not.
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