OK, put another way, the master clock is a lower frequency, the 3 clocks are higher frequency. The three clocks run 1000x faster than the master clock. Could total jitter not be eliminated by comparing all 3 and when the 2 of 3 or 3 of 3 match and don't jive with the master clock, the master is ignored because that's its jitter?
Maybe I don't have the exact solution, but there has to be a way to reduce error by compounding
Also no.
You just create 3 free running clocks that every are synchronized about every 1000 pulses.
A: You cannot create (affordable) clocks that all run at the exact same frequency, let alone share the same phase.
B: When you start comparing and there will always be at least phase differences which one do you pick and will that be the same the next time.
C: Jitter of the slower clock will determine the jitter + at least the one that it picked + at least the 'switch' which passes 1 or the clocks (2 others will always be at least out of phase after 999 pulses which is the decision point.
D: after the decision is made the clocks will sync again and will give a discontinuity in the chosen 'best' clock, resulting in you guessed it... even more jitter every 1000 pulses of the slower clock.
E: The decision circuit (which needs to act fast) will have 3 inputs that will not react at the exact same voltage so will add jitter.
One thing you are correct about.... you don't have the exact solution.
Consider that after the moment 'jitter' has been said to be an issue (decades ago) smart people have tried to come up with solutions and created fixes so that these days jitter (there are many kinds of jitter) is reduced to inaudible levels.
It seems like you try to re-invent the (fly)wheel for clock generation. This while most of the jitter generated in devices is not a clock stability issue (drift and stability is) because the jitter is usually caused by switching components in the circuitry around the clock and connections.