Raindog123
Major Contributor
Triggered by JitterBug thread... How can one actually educate him/herself about "To what degree a modern USB DAC design with (a) an asynchronous USB, (b) internal power stabilization, and (c) internal clock generation would still be affected by the quality of the host's USB?"
Let's say, in a "$100-class" device based on a modern integrated DAC chip:
(1) How badly does the output SQ depend on the cleanliness of the USB 5VDC (ie, how well is it regulated/filtered in the DAC)?
(2) Is the DAC affected by the noise of the host clock (or do the clocks get generated/PLL'ed in the said DAC)?
Is there a concise technical "reference design" description of the state-of-the-art USB DAC interface?
Thanks!
Let's say, in a "$100-class" device based on a modern integrated DAC chip:
(1) How badly does the output SQ depend on the cleanliness of the USB 5VDC (ie, how well is it regulated/filtered in the DAC)?
(2) Is the DAC affected by the noise of the host clock (or do the clocks get generated/PLL'ed in the said DAC)?
Is there a concise technical "reference design" description of the state-of-the-art USB DAC interface?
Thanks!