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Understanding USB interface performance/limitations

Raindog123

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Triggered by JitterBug thread... How can one actually educate him/herself about "To what degree a modern USB DAC design with (a) an asynchronous USB, (b) internal power stabilization, and (c) internal clock generation would still be affected by the quality of the host's USB?"

Let's say, in a "$100-class" device based on a modern integrated DAC chip:
(1) How badly does the output SQ depend on the cleanliness of the USB 5VDC (ie, how well is it regulated/filtered in the DAC)?
(2) Is the DAC affected by the noise of the host clock (or do the clocks get generated/PLL'ed in the said DAC)?

Is there a concise technical "reference design" description of the state-of-the-art USB DAC interface?

Thanks!
 

pozz

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Raindog123

Raindog123

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Are you asking as an engineer or consumer?
Ultimately a consumer... while looking for the answers as an engineer. :)
If I may say so, I am a rather seasoned RF comms/signal processing/HW/SW engineer, and there is a lot of overlap in the two fields' guiding principles... Yet, my goal here is to catchup on the USB technology, admittedly without caring/knowing about its details in the past. @pozz, looks like some of your pointers might be helpful, will go read them. Thanks!
 

pozz

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Ultimately a consumer... while looking for the answers as an engineer. :)
If I may say so, I am a rather seasoned RF comms/signal processing/HW/SW engineer, and there is a lot of overlap in the two fields' guiding principles... Yet, my goal here is to catchup on the USB technology, admittedly without caring/knowing about its details in the past. @pozz, looks like some of your pointers might be helpful, will go read them. Thanks!
Definitely beyond me to answer your question then. There some with deep knowledge of design here that might catch this thread and fill you in.
 

somebodyelse

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The Tone Board docs include a schematic so you can get an idea of things like internal regulation and clocking in a representative DAC. It's no longer class leading, but still pretty good.
 

shal

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riggered by JitterBug thread... How can one actually educate him/herself about "To what degree a modern USB DAC design with (a) an asynchronous USB, (b) internal power stabilization, and (c) internal clock generation would still be affected by the quality of the host's USB?"

Let's say, in a "$100-class" device based on a modern integrated DAC chip:
(1) How badly does the output SQ depend on the cleanliness of the USB 5VDC (ie, how well is it regulated/filtered in the DAC)?
(2) Is the DAC affected by the noise of the host clock (or do the clocks get generated/PLL'ed in the said DAC)?

Is there a concise technical "reference design" description of the state-of-the-art USB DAC interface?

I am computer scientist . I have study usb protocol and I have good comprehension of it but not in the very low (electronic) part

My point of view :

- usb asynchronous brings if well implemented device/host a very very good solution

- the important point is the electric noise between the host (computer) and the device (DAC)


I only considers the asynchronous solution. the synchronous and adaptive solutions is not so good.

Even if asynchronous is in theory not perfect (guarante the bandwidth but not that all usb packet arrives), but in the real life it's OK.
The bad case is if the host (computer) is too slow and cannot fill the buffer of reception of the device (DAC). I have perform test and in my (standard) computer it never happen ..


The electric isolation is of the responsability of the device builder
 
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