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Understanding Chip/Processor Technology

amirm

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This is an article I wrote back in 2012. I thought is still a useful read/primer on one of the key aspects of chip design at the hear of just about every piece of electronics we use today. It is updated for this post.

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Understanding Chip/Processor Technology

A recent technical article on Intel’s new chip reads “Intel's first 22nm CPU, codenamed Ivy Bridge, is off to an odd start….” The article talks as if the 22 nm is the gas mileage for a car and everyone knows what that means. I suspect though most people do not.

The 22 nm is the chip “feature size.” It is a figure of merit for a semiconductor process used to create chips/Integrated Circuits (ICs). It specifies the smallest item that can be “drawn” on a silicon wafer to produce a chip. Think of it as making photocopies of a drawing.

idf_fall_2006_otellini4.jpg

Picture 1: A silicon wafer holding many individual chips that will be separated and packaged into a microprocessor.

At a technical level the feature size is the size of the smallest item which is usually a transistor or a wire interconnecting the same to some other point. Transistors are combined to make simple logic circuits. The simple logic circuits in turn can be combined to make more complicated logic circuits, all the way up to being a microprocessor.

The units of feature size these days is measured in “nanometers” (abbreviated to nm) which is one billionth of a meter. The thickness of human hair is about 40,000 nanometers. So imagine how tiny 22 nm is relative to that! Being able to draw such small feature sizes has taken billions of dollars in research and development. There was a time when 1 micron or 1000 nm was considered a major barrier that may be hard to break. Needless to say, we have gone way past that.

45nm_penny.jpg

Picture 2: Zoomed in view of a microprocessor wafer. Here, each "die" or the part that goes into a microprocessor is about one quarter the size of a US penny.

You may have heard of (Gordon) Moore’s law that says the number of transistors in a chip doubles every two years. He made that prediction in 1965 (!) and thought it would be true for the next 10 years. Here we are decades later and his predictions continue to be true.

It is not often that physics is in your favor but this is one of those rare occasions where if you reduce the feature size, you get the following benefits:
  1. More capacity. Shrink the feature size by a factor of two and you can have four times as many of them. This means more transistors which then translates into faster CPUs, larger memories, more pixels in a camera, etc.

  2. Faster speed. The shorter the distance, the faster electronics go from one point to the other, resulting in higher speed.

  3. Lower Power consumption. Due to shorter distances, less power is needed to convey a signal.
So there is nothing but goodness for customers of these chips. Unfortunately life is not so rosy for the chip designer as reducing the feature size increase the leakage of one circuit onto another. And at any rate, drawing such small circuits and still keeping chip yields high as to have the cost not go up, has become incredibly complex. A new chip manufacturing plant at the state-of-the-art level requires billions of dollars in investment. For this reason, many chip companies today are “fabless” companies meaning they design the chip but then have others manufacture them which can combine everyone’s production to justify such expensive investments. Companies like Intel who have in house chip manufacturing are the exception these days in chip development.

The era of powerful tables and phones would not be upon us without incredible reduction in feature size which with it has brought far lower power consumption, less heat, more computing power, and higher integration of components in smaller spaces.
 
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