TinySine TOSLINKBee SPDIF to I2S Module - ASRC Configuration?

[Rednaxela]

For a little ESP32-based audio project I am trying to work out if this module fits my needs and how.

TOSLINKBee SPDIF to I2S Digital Audio Receiver Module

This TOSLINKBee module can convert SPDIF optical audio singal to I2S output. It has a TOSLINK receiver on the module and two 10 pin 2.0mm male pins. DIR9001PW converts the SPDIF signal to I2S, and CS8421 converts the audio sample rate. TOSLINKBee can automatically adapt to different sampling...

www.tinysineaudio.com

This TOSLINKBee module can convert SPDIF optical audio singal to I2S output. It has a TOSLINK receiver on the module and two 10 pin 2.0mm male pins. DIR9001PW converts the SPDIF signal to I2S, and CS8421 converts the audio sample rate. TOSLINKBee can automatically adapt to different sampling rates devices, from 16bit 44.1KHz to 24bit 96KHz. TOSLINKBee is a I2S slave device, It can work with all our DSP digital amplifiers. If you replace the AudioB Bluetooth module with this TOSLINKBee, the whole amplifier will become a new TOSLINK input amplifier board.

Pins define
5V is input. 3.3v is output


Features:

• Size: 40*35*20mm
• Biphase Input Signal Sampling Frequency (fs) Range: 28 kHz to 108 kHz.
• I2S: Sampling Rate: 44.1KHz to 96KHz
• I2S: Bit per Sample: 16 bit or 24bit
• Input voltage: 5VDC

Basically I am wondering if it can be made to

1. output a fixed 24/96 signal,
2. while at the input side supporting variable bit depths and sample rates.

From the product description it appears so but what is provided is a bit cryptic, and I find myself struggling to connect all the dots.

One thing that's unclear to me is how the unit is to be configured to output either of the supported

• I2S: Sampling Rate: 44.1KHz to 96KHz
• I2S: Bit per Sample: 16 bit or 24bit

To avoid too much TLDR, let me just list my questions.

1. As it is an I2S slave device I take it the first bullet is determined by the I2S master, in my case the ESP32 board, specifically by the *CK signals it generates. Correct?
2. How about the second bullet - is this also set by the I2S master through its *CK rates?
3. If so, how is this in line with what's in section 4.2 - Mode selection (p. 17) of the attached CS8421 data sheet, where it says that output bit depth selection is set and fixed by means of resistors?
4. Has this in this component been set to 24 bit so that 16 bits also fit, or does it not work that way?

Anyone who could shed some light on this? Thanks so much!



Edit: numbered questions