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the new ESP32-C5 and P4 support 16 channel 32 bit TDM in full duplex

IIUC the maximum APLL is 160MHz, while :

Due to hardware limitation, when setting the clock configuration for a slave role, please be aware that <span>i2s_tdm_clk_config_t::bclk_div</span> should not be smaller than 8
IIUC that would mean max bclk of 20MHz - which would be quite slow. 20MHz / 32 bits / 48kHz = 13 channels 32bit TDM max at 48kHz. There are 3 I2S interfaces, but I would be cautious about overall performance of the DMA to fetch so much data.
 
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Thanks for the input. Seems still quite reasonable for a chip normally well documented, cheap, and easy to implement. I would be already very happy if it allows to build a simple usb multichannel DDC/DAC, and seems that someone was already working on it:

 
seems that someone was already working on i
IMHO that code seem quite incomplete - e.g. all out endpoints define async mode, yet I could not find any corresponding async feedback endpoint and its handling.
 
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