SMSL PS 200 internal view

[nanook]

- the gain bandwidth (Gain-bandwidth product = GBW)
- the stabilization time (Settling time)
- the scanning speed (Slew rate = SR)

Hello @ICIETDIYEUR ,
here are my thoughts.
Giving estimations for required Opamp parameters would be nice, but I would need to spend serious time on this.

GBW:
Since the I/V-stage for the ES9039xxx is an inverting amplifier, a large GBW is important to maintain a large loop-gain and thus low distortion for the opamp itself. I haven't compared the THD vs. frequency plots of Opamps with different GBW, but a large GBW should result in a higher frequency where the THD starts to rise.

Sufficient loop-gain also makes sure the transimpedance stage manages to keep its inverting input close to Vref during transients. This is important for the DAC chip that is designed to drive into 0 Ohms and providing a low input resistance of the I/V-stage should improve distortion at higher frequencies where the sample-to-sample amplitude steps get larger.

With a GBW of 10 MHz and e.g. 1k feedback resistor in the I/V-stage, the loop-gain would be 40dB and the input resistance of this stage would be about 10 Ohms at 100kHz. This is ca. 2.5% of the output resistance (390 Ohms) of the ES9039q2m.
This doesn't sound too bad to me, but I cannot judge if this is good enough to make sure it doesn't contribute to THD. And who cares about THD at 100 kHz for listening? For measurement equipment this might be relevant.
Audio: At 10 kHz -> 60dB loop-gain -> 1 Ohm input resistance this should be good enough.

Settling-Time:
Assuming 96kS/s we have a sample every ca. 10us, so my gut-feeling says that the settling time should only be a fraction of this when you are dealing with a signal frequency close to fs/2, where subsequent samples may worst-case have full alternating amplitude. For lower frequencies the amplitude difference the opamp has to settle to is smaller.

I'm not really sure, but doesn't an incomplete settling only result in a tiny deviation in the frequency response? Assume the opamp manages to settle to 99% only (1% error band, thus a very poor requirement) and we are reproducing a sine with a frequency of fs/2, then the amplitude at this frequency would be 99% compared to low frequencies. This would mean the frequency response is ca. 0.1dB down at fs/2 compared to low frequencies. In audio no one would care whereas in a data acquisition application this would be a major flaw - just 7 bits of accuracy.

Slew-Rate:
Power-Bandwidth = Slewrate/(2*pi*Vpeak).
A Slewrate of 20V/us would be good enough for ca. 300 kHz at 7Vrms
Regarding the transient behavior: When dimensioned properly, the feedback capacitor responsible for the LP-filter in the I/V-stage will reduce the necessity of a very fast slewing to moderate values.

I'm afraid we are vastly off-topic, but I'd be curious what e.g. @KSTR and @AnalogSteph do think about my thoughts.
We may as well move this conversation to a different or new thread, if you are interested.

 

[KSTR]

Edit: To say it explicitly: This is why I don't really see the point to use a JFET Opamp in a circuit with a low impedance feedback network like the I/V- stage in a DAC or many other audio circuits. The voltage noise is at least 6dB worse and the JFET cannot benefit from its low current noise when facing a low source impedance.

The OPA828 certainly is excellently suited for I/V duty:
- high GBW
- very high slew-rate
- fast settling, conservative compensation
- very low open-loop output impedance (which is in series with the integrator cap for the initial moment a glitch hits the I/V input)
- good enough voltage noise
- low offset

Everybody loves OPA1612 for its low noise but IMHO the 828 probably is the better part for ESS DAC I/V except for a small noise penalty (and maybe a bit of distortion penalty as well). It just happens to be JFET input. I wouldn't be surprised if someone finds the 828 the better sounding part vs 1612 or 1656 etc

 

[tobyjug]

Is the stated 2 Vrms output on the smsl200 accurate?

 

[staticV3]

Is the stated 2 Vrms output on the smsl200 accurate?

The PS200 puts out 2.2Vrms max:

SMSL PS200 Budget DAC Review

This is a review and measurements of the SMSL PS200 stereo budget DAC. It is on kind loan from a member and costs US $89.99. The unit comes in a lightweight plastic package which allows my rather stiff RCA test cables to yank on it. A simple toggle switch changes inputs. There is an indicator...

www.audiosciencereview.com

 

[tobyjug]

The PS200 puts out 2.2Vrms max:

SMSL PS200 Budget DAC Review

This is a review and measurements of the SMSL PS200 stereo budget DAC. It is on kind loan from a member and costs US $89.99. The unit comes in a lightweight plastic package which allows my rather stiff RCA test cables to yank on it. A simple toggle switch changes inputs. There is an indicator...

www.audiosciencereview.com

Thanks.

 

[nanook]

The OPA828 certainly is excellently suited for I/V duty

I agree, the OPA828 is indeed a very remarkable opamp too, so it's worth considering dropping a few dB S/N. The flat Zout @ open-loop (ca. 13 Ohms from 1Hz to 100MHz according to the datasheet) is a very nice property.
It would be really interesting if this opamp helps to alleviate the distinct hump seen in THD vs. level plots of the ES9039q2m.

 

[jkim]

It would be really interesting if this opamp helps to alleviate the distinct hump seen in THD vs. level plots of the ES9039q2m.

I wonder what you mean by "the distinct hump seen in THD vs. level plots of the ES9039q2m."

In the case of the E1DA 9039S, THD is vanishingly low for the entire signal levels, just 24 dB higher (in the worst case) than its extremely low noise floor measurable by the Cosmos ADCiso.

In any case, I wonder if @IVX considered the OPA(2)828 in his development of the 9039S.

 

[ICIETDIYEUR]

Hi.

Thank you for your feedback

Here's my thoughts on a specific case, but they apply to other DAC chips ->

Determine the minimum settling time for the operational amplifier required for the circuit to operate properly.

Example: The PCM1794 chip will be 24 bits - 96 kHz - 768 fs, or the maximum possible fsck (system clock frequency) = the same for the maximum at 192 kHz, with a maximum of 384 fs according to the DATASHEET.

Then, the maximum frequency reached for 96 kHz will be: 96 kHz x 768 fs = 73.728 MHz.
We need the concept of time to determine the settling time, so we assume: 1/F = 13 ns.

Now, a complete swing is 24 bits in this example.
So, the waveform will have 12 bits in 'one direction'.
We then obtain: 13ns x 12 = 156ns, the MAXIMUM required for the operational amplifier's 'Settling Time' to ensure proper operation of the circuit in question at this operating frequency.

Is this correct ?

 

[nanook]

I wonder what you mean by "the distinct hump seen in THD vs. level plots of the ES9039q2m."

I was referring to my measurements on the SMSL D-6s when getting accustomed to pkane's "Multitone Analyzer" software:

SMSL D-6s Balanced DAC Review

Meridian certainly has made the most out of this chip. But of course the PCM5102 is not comparable to the ES9039q2m and the D-6s is a well executed design. Yes, there are pops from time to time between different songs, but they are not loud at all in my system. WiiM Pro - > Coax input of D-6s...

audiosciencereview.com

The posts following mine do confirm the observed behavior.
For some reason I didn't see such a hump on the SMSL DO400 (1x ES9039 PRO) or the USB bus powered SMSL PO100 AK (1x AK4493).

My first set of measurements were plotted against the "received level" (I was not yet familiar with the Multitone Analyzer software).
The measurements on my second D-6s were plotted against the "transmitted level" (post #918).

Note: I'm aware that I'm looking deep into the noise floor when looking at THD with a fairly long FFT (compare to the white trace THD+N), so certainly nothing to worry about in terms of audibility. But for measurement freaks like me, this is interesting behavior.

 

[jkim]

I was referring to my measurements on the SMSL D-6s when getting accustomed to pkane's "Multitone Analyzer" software:

SMSL D-6s Balanced DAC Review

Meridian certainly has made the most out of this chip. But of course the PCM5102 is not comparable to the ES9039q2m and the D-6s is a well executed design. Yes, there are pops from time to time between different songs, but they are not loud at all in my system. WiiM Pro - > Coax input of D-6s...

audiosciencereview.com

The posts following mine do confirm the observed behavior.
For some reason I didn't see such a hump on the SMSL DO400 (1x ES9039 PRO) or the USB bus powered SMSL PO100 AK (1x AK4493).

My first set of measurements were plotted against the "received level" (I was not yet familiar with the Multitone Analyzer software).
The measurements on my second D-6s were plotted against the "transmitted level" (post #918).

Note: I'm aware that I'm looking deep into the noise floor when looking at THD with a fairly long FFT (compare to the white trace THD+N), so certainly nothing to worry about in terms of audibility. But for measurement freaks like me, this is interesting behavior.

Of course, that is the "worst case" I mentioned in my reply, which is still one of the lowest levels of all DACs we've seen so far. Most of the harmonic products below that "hump" signal level essentially touch the noise floor. We're talking about not only inaudible levels of harmonic products from DACs but also measurably the lowest THD levels. Sure, we could still call it a "hump", though.

EDIT. Here are my measurements of the E1DA 9039S:

And this is an FFT of 1 kHz sinusoid @ 0 dBFS measured with the APU's notch filter:

 

[nanook]

In any case, I wonder if @IVX considered the OPA(2)828 in his development of the 9039S.

The dual OPA828, OPA2828, is almost double the price of an OPA1612, so there must be good reasons.
And I'd expect that noise will up by a couple of dB.

 

[jkim]

The dual OPA828, OPA2828, is almost double the price of an OPA1612, so there must be good reasons.
And I'd expect that noise will up by a couple of dB.

Sure.
@KSTR also says,

...(and maybe a bit of distortion penalty as well).

Then, what aspect of a ES9039q2m-based DAC would the use of the OPA828 improve?

 

[nanook]

Then, what aspect of a ES9039q2m-based DAC would the use of the OPA828 improve?

I think @KSTR is referring to investigations he did on the "ESS IMD hump". From what I remember glitches from the output of the DAC chip were under suspect. Glitches that were beyond what the opamp in the I/V-stage could handle without passive filtering ahead (or in) the I/V-stage. But I'm not sure if this still is the final conclusion.

This is (one of) the thread(s): https://www.audiosciencereview.com/...-hump-revisited-khadas-tone-board-v1-3.30136/

The ES9039xxx is a lot more well-behaved compared to the ES9038xxx (see e.g. https://archimago.blogspot.com/2024/04/detailed-thdn-vs-output-level.html), but the slight hump that still is visible in some ES9039q2m measurements may eventually have the same origin.

 

[jkim]

I think @KSTR is referring to investigations he did on the "ESS IMD hump". From what I remember glitches from the output of the DAC chip were under suspect. Glitches that were beyond what the opamp in the I/V-stage could handle without passive filtering ahead (or in) the I/V-stage. But I'm not sure if this still is the final conclusion.

This is (one of) the thread(s): https://www.audiosciencereview.com/...-hump-revisited-khadas-tone-board-v1-3.30136/

The ES9039xxx is a lot more well-behaved compared to the ES9038xxx (see e.g. https://archimago.blogspot.com/2024/04/detailed-thdn-vs-output-level.html), but the slight hump that still is visible in some ES9039q2m measurements may eventually have the same origin.

Right, even the DACs with no clear ESS hump in Amir's AP IMD+N measurements show a slight, noticeable hump when you plot pure IMD or THD vs. output level, just like I showed in my post above---my Topping D50 III has essentially the same THD curve as the E1DA 9039S.

But compared to the clear ESS hump cases, these humps are negligibly low. Right, it is likely that they share the same origin, though.

By the way, have you read the recent RAA article about the ESS hump? I guess the origin lies in the DAC chip's design itself, not surrounding circuits.

 

[nanook]

By the way, have you read the recent RAA article about the ESS hump? I guess the origin lies in the DAC chip's design itself, not surrounding circuits.

Thanks, no I had not yet come across this article.

Do you know a DAC using the ES9039q2n that has the I/V-stage implemented according to the proposal from the ES9039PRO datasheet (attached)?
This topology makes sure, that the inverting amplifiers reference against the common- mode voltage of the differential outputs. And it eliminates the need to adjust offset.

The D-6s uses the circuit that is typical for SMSL, they generate VDDA/2 buffer it, provide some offset adjustment and use it as reference for the I/V opamps.

 

[jkim]

Do you know a DAC using the ES9039q2n that has the I/V-stage implemented according to the proposal from the ES9039PRO datasheet (attached)?
This topology makes sure, that the inverting amplifiers reference against the common- mode voltage of the differential outputs. And it eliminates the need to adjust offset.

The D-6s uses the circuit that is typical for SMSL, they generate VDDA/2 buffer it, provide some offset adjustment and use it as reference for the I/V opamps.

No, I do not. The schematic shown in the ES9039(M)PRO must be what is referred to by 'Note 2' of the recommended output stage schematic in the ES9039Q2M datasheet. Right? See attached.

By the way, since most DAC product developers rely on the reference design shown in the datasheet or development board, I guess DACs based on the ES9039(M)PRO may show different THD/IMD behavior. Have you seen any THD/IMD vs. output level measurements of such DACs?

 

[IVX]

Right, OPA2828 looks way too noisy for that purpose.

 

[nanook]

The schematic shown in the ES9039(M)PRO must be what is referred to by 'Note 2' of the recommended output stage schematic in the ES9039Q2M datasheet. Right?

Yes, I think this is meant by note 2. It's a nice circuit since it very efficiently removes common-mode noise from the XLR output. As a bonus, it does not need some sort of offset adjustment.
This circuit topology - and others - are discussed here: https://www.diyaudio.com/community/...servo-as-shown-by-es9039pro-datasheet.397186/

The circuit in the D-6s and the DO400 that I have is much simpler like described above (I posted a simplified schematic of the D-6s I/V-stage here: https://audiosciencereview.com/foru...l-d-6s-balanced-dac-review.48813/post-1913251)

 

[Luca Sorrentino]

The linearity is nailed down to -120dBr, that is 20bits:

Hi Flo, how did you do this test, I suppose with REW, maybe there something obvious that does not occurs to me but I'm not able to do it. I'm lost in stepped leves, but in the overlays->linearity plot I can't see nothing.

 

[NTTY]

Hi Flo, how did you do this test, I suppose with REW, maybe there something obvious that does not occurs to me but I'm not able to do it. I'm lost in stepped leves, but in the overlays->linearity plot I can't see nothing.

Yes, go to RTA, click "Stepped Sine", select "THD vs Level", and run it from -120dBFS to -60dBFS (it's enough).

Once the test is finished, go back to the main window, SPL & Phase, select dBr, zoom, and you get the below:

Red line is what was requested by the generator, green one is what was seen at the input of the ADC, and shown as "Linearity" here.

With the PS200, I got less than 0.1dB variation at -120dBFS, meaning 20bits of linearity.

Cheers