Hello Everyone,
This is a review and measurements of the SMSL PO100 PRO USB Digital Interface.
It was already reviewed almost 4 years ago by @VintageFlanker, but only in analog domain, via an external DAC. I'll be testing in digital domain mainly.
A Digital to Digital Converter acts as a bridge between a computer and whatever device with digital inputs (DAC, preamp, integrated amp, powered speakers, etc...) you wish to use.
There are multiple business cases for this device, and mine is to use it to send high quality digital signal to a device under test. So it will be my digital generator, main advantage being that I can powered it from the PC directly.
It is very important for me to ensure that the digital output from this SMSL is of very high quality and unaltered, if possible, or that I know about the possible flaws and how to mitigate them.
User experience
It can't be simpler to use, I did not have to install a driver (Windows 11) although SMSL site says I have to, and I guess this is because I already installed a SMSL compatible driver in the past.
There are two buttons to select UAC-1 (for backward compatibility) or AUC-2, and one to change the pin allocation of the I2S (HDMI connector) which I did not use.
SMSL PO100 PRO - Measurements (Digital)
To measure the PO100 PRO, I used a Motu Ultralite Mk5 pro interface which has digital inputs (coax and Toslink). The software is REW, as always for me.
So the setup is simple, Computer (REW) -> SMSL PO100 PRO -> Toslink 3m cable -> Motu Mk5 -> Computer (REW).
The Motu requires I use its ASIO driver in REW, while the SMSL requires the Java one, so I had two instances of REW, one acting as the Generator and the other as the Analyzer. That means I can't run sweeps, but you'll see it's not an issue.
Let's start with the standard 1kHz test tone at 0dBFS (24bits data) without dither, the sampling rate is 44.1kHz:
Look at the y-axis that goes way below (-190dBr!) what you usually see with Amir's review. This is because we don't have analog noise here, it's all in digital domain.
Of course you see some grass at the bottom of the graph and that what we call "quantization noise". These are due to rounding errors when sampling the continuous signal into a digital one. Since this is 24bits, we have "only" 2^24 = 16'777'216 values (integers) to represent all possible values of an analog voltage swing. And sometimes the ideal value would need to be in between two possible integer values out of the 16M+ available. When that happens, it generates an inevitable error, and that translates into that type of distorsion, or better called "quantization noise".
Additional interesting fact is that these rounding errors can accumulate and show themselves as low level random noise or as some sort of distorsion that you see above.
As a proof, let me run the same test, but with a sine tone that is a prime number, instead of 1kHz. Here you go with a 997Hz test tone @0BFS:
See the difference? This time you see a low level noise that appears random. It hurts less you eyes. But that is the same reason, it’s because of rounding errors, quantization noise. Why does it spread better than 1kHz? This is because a 1kHz sine generates much less PCM unique subcodes than the 997Hz one. Having more unique PCM 24bits codes means the rounding errors are very variable and so the resulting distortion that they generate better spreads and shows as kind of random noise.
Actually, this is an interesting fact because it can influence the value of what is called "Spurious Free Dynamic Range" (SFDR). The SFDR is the ratio of the amplitude of the main output signal (the fundamental) to the amplitude of the next largest unwanted distortion or noise component (the "spurious" tone or spur) (Analog Devices).
When the PCM subcodes are limited, we are likely to see a decrease of the SFDR. This is of no importance for reproducing music, but it is for me as wanting to use this device as a high precision generator. Look at the below:
From that, you see an interest to go for the 997Hz test tone. Well, ok, this is not an issue in digital domain, since both SFDR are way better than the best DAC out there. But let's do the same with 16bits PCM:
Ouch, you get the interest, right?
Back to 24bits... The AES standard recommends to use dither (for that reason I guess) when generating test signals. Let's do that with the 1kHz test tone:
Yes, nice, but we lost one bit of resolution because that is what the dither noise consumes. So the dither (low level random noise) indeed allows for a better spreading of the quantization noise, at the expense of limiting the potential full resolution. Again, no big deal with 24 bits since all DACs and ADCs will be limited way before that in 24bits. But it is a different view in 16bits. And this is the reason why I use a 999.91Hz test tone for my tests of CD Players, because it generates a lot of unique PCM subcodes in very short time, spreading well the quantization noise and thus offering the best SFDR we can expect in 16bits PCM.
With all of the above, maybe you've learned something new, or not. But I guess you get that the digital output of the SMSL PO100 PRO is very precise since it is the one I used for all measurements.
----
We can still chalenge it, at least on jitter perspective, though. This is the standard J-test at 24bits (44.1kHz):
Blue trace is from the PO100 and red one is from the WAV file. They are the same meaning no jitter. Actually, you also never see that trace so clean from Amir's review, and that is because the low level signal is hidden by the analog noise of the DAC. Here is the same jitter test with the Topping D50III that is an excellent DAC:
See how the analog noise covers the low level digital component of the Jitter Test?
And this is an opportunity to remember what the jitter test is made of. There are two components:
Since 2^24 = 16'777'216, the truth table of the PCM code is the below (24bits):
This is a signed code where the first bit (called Most Significant Bit - MSB) is the bit of the sign. It is the one that has the most significant weight. The last bit of the code is the Low Significant Bit (LSB) because it is the one representing the smallest possible value (1/8388608).
Note that the code is asymmetric because the 0 value is considered positive. So we have one less value to represent the positive swing compared to the negative one.
Note also that from -1 to 0, all bits of the code will flip. This is what the Jitter Test leverages as a "stressor". So, the low Frequency component of the Jitter Test is a square wave that uses only the negative 1LSB and so the low level square forces a constant flip as below:
00000000000000000000000 : 0
11111111111111111111111 : -1
The frequency of the square is 1/192fs to align the SPDIF (or AES3) format that is based on blocks of 192 frames.
----
Now, let me have some additional fun with what Stereophile was calling the 3DC test. This is a test were only the two lowest negative and positive levels are stimulated. If you look again at the table the I previously showed, it means we create a sine that invoques only 3 PCM codes, as per the below:
00000000000000000000001 : +1
00000000000000000000000 : 0
11111111111111111111111 : -1
Not only this is the smallest symmetrical possible signal in 24 bits PCM, it is again generating a regular flip of all bits from 0 to 1. Very first R2R DACs did not like that, reason for the test. Here, we don't test a DAC as we stay in digital domain. But if the interface would be modifying the digital content, we would see a different code.
The digital level of that signal (in dBFS) is calculated by the formula 20log(2/16'777'216)=-138.47dBFS
To test that the code is unchanged, we simply look and the result in time domain. Since this signal is a constant change between only three levels, you get the same in time domain:
With only the lowest bit (LSB) used, we get three "DC" levels, of constant amplitude since in it impossible to represent a sine with only one bit and so only 3 level -1,0,+1 (half a period for the 0-cross). What is good with this test is that any modification on a single bit in the code would generate a massive error in the amplitude showing itself immediately. Here we get what we want, ie bit perfect.
The ringing you see is due to the Gibbs phenomenon.
I zoomed at max on REW's scope, but it's still low amplitude because that signal is extremely low and something we can't see in analog domain. The same with 16bits PCM is the below:
----
Last and not least, as I use for my regular reviews of CD Players, my ultimate proof of "perfect" digital output is when I reuse the intersample overs test at 5512.50Hz, with a phase shift of 67.5°. This signal generates an overshoot of +0.69dB. And so, if the signal would be modified before being sent over SPDIF (by an ASRC for instance), it would show either a reduction of amplitude or we'd see some sort of saturation/increase of noise/distorsion. So, here we go (note this is a 16bits test):
And yeah, we get what we want. No distortion and the dashboard shows +0.69dBFS as expected. No ASRC on the digital path here. SNR is only 95.6dB because there is rectangle dither in this test file (consuming half of a bit out of the 16 available).
----
EDIT: I forgot to add that the clock deviation is lower than what I can measure, and that means better than 0.2ppm. I’ll add the corresponding trace later.
SMSL PO100 PRO feeding a DAC
To finalize this test, I still wanted to check the analog output of a DAC fed by the SMSM PO100 PRO. I used the Topping D50III that Amir reviewed.
This is the result at 24 bits with the standard 1kHz test tone (with Dither):
Note that I changed the y-axis to max -170dBr instead of -200dBr you saw before.
This is an excellent result (123.4dB SINAD), a little better than what Amir measured in his review (same bandwidth of analysis to include noise), I got less noise but a little more distortion. The SMSL PO100 PRO is far from its maximum but the results out of the Topping D50III puts it where it is: at the top of Amir's DACs ranking.
Conclusion
No surprises that this is a flawless device, but now you know and can say why
With such precision, the potential issues might come from the Software and associated setup that you use.
Enjoy your WE!
Flo
This is a review and measurements of the SMSL PO100 PRO USB Digital Interface.
It was already reviewed almost 4 years ago by @VintageFlanker, but only in analog domain, via an external DAC. I'll be testing in digital domain mainly.
This device is digitally "perfect" and its limits are the Software and drivers you'll be using with it, not its "hardware" performances. So this review will be more kind of an opportunity to learn more about PCM digital signal, rather than just a series of standardized measurement graphs, which would be boring because all state of the art.
A Digital to Digital Converter acts as a bridge between a computer and whatever device with digital inputs (DAC, preamp, integrated amp, powered speakers, etc...) you wish to use.
There are multiple business cases for this device, and mine is to use it to send high quality digital signal to a device under test. So it will be my digital generator, main advantage being that I can powered it from the PC directly.
It is very important for me to ensure that the digital output from this SMSL is of very high quality and unaltered, if possible, or that I know about the possible flaws and how to mitigate them.
User experience
It can't be simpler to use, I did not have to install a driver (Windows 11) although SMSL site says I have to, and I guess this is because I already installed a SMSL compatible driver in the past.
There are two buttons to select UAC-1 (for backward compatibility) or AUC-2, and one to change the pin allocation of the I2S (HDMI connector) which I did not use.
SMSL PO100 PRO - Measurements (Digital)
To measure the PO100 PRO, I used a Motu Ultralite Mk5 pro interface which has digital inputs (coax and Toslink). The software is REW, as always for me.
So the setup is simple, Computer (REW) -> SMSL PO100 PRO -> Toslink 3m cable -> Motu Mk5 -> Computer (REW).
The Motu requires I use its ASIO driver in REW, while the SMSL requires the Java one, so I had two instances of REW, one acting as the Generator and the other as the Analyzer. That means I can't run sweeps, but you'll see it's not an issue.
Let's start with the standard 1kHz test tone at 0dBFS (24bits data) without dither, the sampling rate is 44.1kHz:
Look at the y-axis that goes way below (-190dBr!) what you usually see with Amir's review. This is because we don't have analog noise here, it's all in digital domain.
Of course you see some grass at the bottom of the graph and that what we call "quantization noise". These are due to rounding errors when sampling the continuous signal into a digital one. Since this is 24bits, we have "only" 2^24 = 16'777'216 values (integers) to represent all possible values of an analog voltage swing. And sometimes the ideal value would need to be in between two possible integer values out of the 16M+ available. When that happens, it generates an inevitable error, and that translates into that type of distorsion, or better called "quantization noise".
Additional interesting fact is that these rounding errors can accumulate and show themselves as low level random noise or as some sort of distorsion that you see above.
As a proof, let me run the same test, but with a sine tone that is a prime number, instead of 1kHz. Here you go with a 997Hz test tone @0BFS:
See the difference? This time you see a low level noise that appears random. It hurts less you eyes. But that is the same reason, it’s because of rounding errors, quantization noise. Why does it spread better than 1kHz? This is because a 1kHz sine generates much less PCM unique subcodes than the 997Hz one. Having more unique PCM 24bits codes means the rounding errors are very variable and so the resulting distortion that they generate better spreads and shows as kind of random noise.
Actually, this is an interesting fact because it can influence the value of what is called "Spurious Free Dynamic Range" (SFDR). The SFDR is the ratio of the amplitude of the main output signal (the fundamental) to the amplitude of the next largest unwanted distortion or noise component (the "spurious" tone or spur) (Analog Devices).
When the PCM subcodes are limited, we are likely to see a decrease of the SFDR. This is of no importance for reproducing music, but it is for me as wanting to use this device as a high precision generator. Look at the below:
From that, you see an interest to go for the 997Hz test tone. Well, ok, this is not an issue in digital domain, since both SFDR are way better than the best DAC out there. But let's do the same with 16bits PCM:
Ouch, you get the interest, right?
Back to 24bits... The AES standard recommends to use dither (for that reason I guess) when generating test signals. Let's do that with the 1kHz test tone:
Yes, nice, but we lost one bit of resolution because that is what the dither noise consumes. So the dither (low level random noise) indeed allows for a better spreading of the quantization noise, at the expense of limiting the potential full resolution. Again, no big deal with 24 bits since all DACs and ADCs will be limited way before that in 24bits. But it is a different view in 16bits. And this is the reason why I use a 999.91Hz test tone for my tests of CD Players, because it generates a lot of unique PCM subcodes in very short time, spreading well the quantization noise and thus offering the best SFDR we can expect in 16bits PCM.
With all of the above, maybe you've learned something new, or not. But I guess you get that the digital output of the SMSL PO100 PRO is very precise since it is the one I used for all measurements.
----
We can still chalenge it, at least on jitter perspective, though. This is the standard J-test at 24bits (44.1kHz):
Blue trace is from the PO100 and red one is from the WAV file. They are the same meaning no jitter. Actually, you also never see that trace so clean from Amir's review, and that is because the low level signal is hidden by the analog noise of the DAC. Here is the same jitter test with the Topping D50III that is an excellent DAC:
See how the analog noise covers the low level digital component of the Jitter Test?
And this is an opportunity to remember what the jitter test is made of. There are two components:
- The High-Frequency Component (The Carrier): The primary signal is a high-frequency tone that sits exactly at one-quarter of the sampling frequency (fs/4).
- The Low-Frequency Component (The Stressor): The second part is a low-frequency square wave designed to manipulate the Least Significant Bit (LSB), which is the smallest possible bit value in the digital word.
Since 2^24 = 16'777'216, the truth table of the PCM code is the below (24bits):
| PCM CODE | Signed Decimal value |
| 01111111111111111111111 | +8'388'607 |
| ... | ... |
| 00000000000000000000001 | +1 |
| 00000000000000000000000 | 0 |
| 11111111111111111111111 | -1 |
| ... | ... |
| 10000000000000000000000 | -8'388'608 |
This is a signed code where the first bit (called Most Significant Bit - MSB) is the bit of the sign. It is the one that has the most significant weight. The last bit of the code is the Low Significant Bit (LSB) because it is the one representing the smallest possible value (1/8388608).
Note that the code is asymmetric because the 0 value is considered positive. So we have one less value to represent the positive swing compared to the negative one.
Note also that from -1 to 0, all bits of the code will flip. This is what the Jitter Test leverages as a "stressor". So, the low Frequency component of the Jitter Test is a square wave that uses only the negative 1LSB and so the low level square forces a constant flip as below:
00000000000000000000000 : 0
11111111111111111111111 : -1
The frequency of the square is 1/192fs to align the SPDIF (or AES3) format that is based on blocks of 192 frames.
----
Now, let me have some additional fun with what Stereophile was calling the 3DC test. This is a test were only the two lowest negative and positive levels are stimulated. If you look again at the table the I previously showed, it means we create a sine that invoques only 3 PCM codes, as per the below:
00000000000000000000001 : +1
00000000000000000000000 : 0
11111111111111111111111 : -1
Not only this is the smallest symmetrical possible signal in 24 bits PCM, it is again generating a regular flip of all bits from 0 to 1. Very first R2R DACs did not like that, reason for the test. Here, we don't test a DAC as we stay in digital domain. But if the interface would be modifying the digital content, we would see a different code.
The digital level of that signal (in dBFS) is calculated by the formula 20log(2/16'777'216)=-138.47dBFS
To test that the code is unchanged, we simply look and the result in time domain. Since this signal is a constant change between only three levels, you get the same in time domain:
With only the lowest bit (LSB) used, we get three "DC" levels, of constant amplitude since in it impossible to represent a sine with only one bit and so only 3 level -1,0,+1 (half a period for the 0-cross). What is good with this test is that any modification on a single bit in the code would generate a massive error in the amplitude showing itself immediately. Here we get what we want, ie bit perfect.
The ringing you see is due to the Gibbs phenomenon.
I zoomed at max on REW's scope, but it's still low amplitude because that signal is extremely low and something we can't see in analog domain. The same with 16bits PCM is the below:
----
Last and not least, as I use for my regular reviews of CD Players, my ultimate proof of "perfect" digital output is when I reuse the intersample overs test at 5512.50Hz, with a phase shift of 67.5°. This signal generates an overshoot of +0.69dB. And so, if the signal would be modified before being sent over SPDIF (by an ASRC for instance), it would show either a reduction of amplitude or we'd see some sort of saturation/increase of noise/distorsion. So, here we go (note this is a 16bits test):
And yeah, we get what we want. No distortion and the dashboard shows +0.69dBFS as expected. No ASRC on the digital path here. SNR is only 95.6dB because there is rectangle dither in this test file (consuming half of a bit out of the 16 available).
----
EDIT: I forgot to add that the clock deviation is lower than what I can measure, and that means better than 0.2ppm. I’ll add the corresponding trace later.
SMSL PO100 PRO feeding a DAC
To finalize this test, I still wanted to check the analog output of a DAC fed by the SMSM PO100 PRO. I used the Topping D50III that Amir reviewed.
This is the result at 24 bits with the standard 1kHz test tone (with Dither):
Note that I changed the y-axis to max -170dBr instead of -200dBr you saw before.
This is an excellent result (123.4dB SINAD), a little better than what Amir measured in his review (same bandwidth of analysis to include noise), I got less noise but a little more distortion. The SMSL PO100 PRO is far from its maximum but the results out of the Topping D50III puts it where it is: at the top of Amir's DACs ranking.
Conclusion
No surprises that this is a flawless device, but now you know and can say why
With such precision, the potential issues might come from the Software and associated setup that you use.
Enjoy your WE!
Flo
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