Indeed, I wonder if ESS' secret datasheet has any measurements like we are performing.
Most of my experience is with digital integrated circuits. There the post-silicon verification consists of a lot of testing within the design 'box' of high/low limits for power supply voltage; clock rate; and temperature. In general, analog or mixed signal chips have several temp coefficients to balance in the design. Digital chips have very small geometries (7 nm, anyone?) and requisite tight process controls and physical design niceties that need to be well handled to keep the voltage/clock/temp box large enough to be practicable.
That's a long winded way of saying that having tight temp windows on a precision analog design is *not* a surprise.
Mounting technique (within the package and outside the package) and package type have major effects on die temp. its all interrelated.
Generally speaking, a lot of specs are publicly presented for nominal conditions. ESS should have a fairly precise characterization of the device's behavior across temp variations. Plus process variations do occur and they may be 'binning' parts based upon temp sensitivity.