- Joined
- Jul 21, 2020
- Messages
- 84
- Likes
- 127
The M500 oscillator has to lock on the clock signal of the source (for example toslink). This is realized in the DAC by a digital phase-locked loop (DPLL). In the first edition of the M500 the lock-in range (bandwidth) was fixed. This lead to problems with some cheaper (too jittery) Toslink outputs of TVs. M500 lost the lock-in and periods were skipped leading to an audio artefact. To solve this problem there is now this option in the menu. If you have a good source (stable clock - low jitter) you can lower this value. If you experience problems (drop outs) you can increase the value.What's the DPLL setting? Default value is 7.
Last edited: