The clocks on the DAC are for the USB section. If you're concerned about jitter, use the USB interface, as that is what was measured to have low jitter.
IMHO and contrary to the perpetual disinfo you get from this site, all the other inputs do not "reclock" -- jitter in, garbage out. Reclocking is in and of itself potentially problematic, although there are claims that a "dual PLL" design fixes such issues. I have not seen a consumer DAC with this feature other than the ADI-2 "steadyclock" (TBD -- does it suffer from the problems alluded to in the paper about dual PLL reclocking i posted previously).\
Does the DX7Pro /M500/etc have a "steadyclock" -- if it did it would have an FPGA and a bunch of other crap and Topping or SMSL would have pretty marketing pictures and statements about it as a feature.
On pondering the role of the third 100Mhz fancy "femptosecond" clock, I'm pretty sure now the DX7Pro does not literally "reclock" but it does have a simple single-PLL circuit to de-jitter the SPDIF and Optical inputs. The other two crystal oscillators support sampling rates in multiples of 44.1k and 48k over the USB interface.
See:
https://www.audiosciencereview.com/...c-and-headphone-amp-reviewed.9446/post-262644
This standard way of doing an SPDIF/Optical interface gives some jitter immunity, although it is disputed that single phase lock loop-based jitter reduction is "bit perfect" or without its own artefacts. The fact that ADI2 uses an expensive FPGA to implement something more special than what would be available in a cheap off the shelf chip like WM8804/8805 suggests they're doing something a lot fancier than a single PLL in their "steadyclock" implementation (it should alert you that they were willing to spend big $$$ on low-jitter clocking, and still come up with a better sounding DAC even with non SOTA DAC chip, b/c that's how important jitter is to sound quality improvement). Perhaps it is their version of the dual PLL design from AXON or something to address the single PLL shortcomings and the errors it introduces:
https://s3t.it/data/uploads/docs/di...-in-high-resolution-digital-audio-systems.pdf
Why Jitter matters in high resolution digital audio systems
A description of jitter analyses and jitter reduction in a 24bit/96k Broadcast 4 channel D/A converter.
Peter Schut Axon Digital Design BV
"Several plots of the high-resolution jitter analyzer used by Axon Digital Design will show how both data induced, and interface induced jitter artifacts, work their way through normal single PLL clock recovery circuits. Jitter in the D/A process can lower the resolution in the reconstructed analog domain to levels that are clearly audible and demonstrate to every audio engineer the harm to system integrity and system transparency.
Clock Jitter
The jitter responsible for the loss of resolution and distortion in the analog reconstructed signal is clock jitter. This clock jitter is either the wordclock or masterclock of the D/A converter chip. Depending on the conversion principle used by the actual converter, either the masterclock or wordclock needs to be jitter free. The jitter measured at this point is the timing deviation of the transitions compared to an ideal clock. These timing variations are divided into a jitter frequency and amplitude. Examining the eye pattern of these clocks with an oscilloscope can tell you something of the peak to peak value, but gives you no information of the jitter frequency. Using an oscilloscope for jitter amplitudes lower than 1ns is almost impossible. So we need a dedicated jitter analyzer. The unit Axon is using has an intrinsic jitter of 0.4 ps RMS for a clock frequency of 12.288 MHz (=256 x 48 kHz) and 1.2 ps for 192 kHz (=4 x 48 kHz). The theoretical degradation for high frequencies (>5kHz) is shown in table1. This table tells nothing of the audibility of the jitter present, just the measurable artifact that jitter has on discrete frequencies. If we look at the rise in noise floor we get the values shown in table 2. Rev. 1
jitter 8ps 16ps 32ps 64ps 128ps 256ps 05ns 1ns 2ns 4ns
Resolution in bits 20 19 18 17 16 15 14 13 12 11
Table 1: maximum jitter for a given resolution
jitter 1ns 2ns 4ns 8ns 16ns
Noise floor -105dB -97dB -90dB -84dB -79dB
Table 2: maximum jitter for a given noise-floor
High frequency jitter causes more audible degradation than low frequency jitter. High frequency signals are also more degraded by a certain amount of jitter than low frequency signals."