• WANTED: Happy members who like to discuss audio and other topics related to our interest. Desire to learn and share knowledge of science required. There are many reviews of audio hardware and expert members to help answer your questions. Click here to have your audio equipment measured for free!

Sabaj D5 vs. SMSL M500 vs. Topping DX7 Pro: measurement comparison

VintageFlanker

Major Contributor
Forum Donor
Joined
Sep 20, 2018
Messages
4,942
Likes
19,694
Location
Paris
I am curious to see comparison of unbalanced SINAD performance of all these three DACs.
Already measured (Except the DX7 PRO, but I won't be surprised it is on par):

Sabaj D5 DAC and Headphone Amplifier RCA Audio Measurements.png


SMSL M500 DAC and Headphone Amplifier RCA Cold Audio Measurements.png
 

NielsMayer

Active Member
Joined
May 31, 2019
Messages
102
Likes
66
Location
Newport Beach, CA
http://www.audiophilleo.com/docs/Dunn-AP-tn23.pdf
Application and Technical Support for Audio Precision
Jitter Theory
By Julian Dunn
...
Audibility considerations

It is one thing to be able to identify and measure sampling jitter. But how can we tell if there is too much? A recent paper by Eric Benjamin and Benjamin Gannon describes practical research that found the lowest jitter level at which the jitter made a noticeable difference was about 10 ns rms. This was with a high level test sine tone at 17 kHz. With music, none of the subjects found jitter below 20 ns rms to be audible.7 This author has developed a model for jitter audibility based on worst case audio single tone signals including the effects of masking.8 This concluded: “Masking theory suggests that the maximum amount of jitter that will not produce an audible effect is dependent on the jitter spectrum. At low frequencies this level is greater than 100 ns, with a sharp cut-off above 100 Hz to a lower limit of approximately 1 ns (peak) at 500 Hz, falling above this frequency at 6 dB per octave to approximately 10 ps (peak) at 24 kHz, for systems where the audio signal is 120 dB above the threshold of hearing.” In the view of the more recent research, this may be considered to be overcautious. However, the consideration that sampling jitter below 100 Hz will probably be less audible by a factor of more than 40 dB when compared with jitter above 500 Hz is useful when determining the likely relative significance of low- and high-frequency sampling jitter.

"Eric Benjamin and Benjamin Gannon, "Theoretical and Audible Effects of Jitter on Digital Audio Quality", Preprint 4826 of the 105th AES Convention, San Francisco, September 1998"

Or you can go back to 1974, monophonic, and no consideration whatsoever of where positional information is encoded in an audio signal needing to reconstruct a stereo image:
http://downloads.bbc.co.uk/rd/pubs/reports/1974-11.pdf
 
Last edited:

MediumRare

Major Contributor
Forum Donor
Joined
Sep 17, 2019
Messages
1,949
Likes
2,275
Location
Chicago
“Masking theory suggests that the maximum amount of jitter that will not produce an audible effect is dependent on the jitter spectrum. At low frequencies this level is greater than 100 ns, with a sharp cut-off above 100 Hz to a lower limit of approximately 1 ns (peak) at 500 Hz, falling above this frequency at 6 dB per octave to approximately 10 ps (peak) at 24 kHz, for systems where the audio signal is 120 dB above the threshold of hearing.”
How do we relate the 1 ns figure to dB units reported by Amir?
 

Kane1972

Active Member
Joined
Dec 11, 2018
Messages
298
Likes
103
Be great if a photo of the innards of all the DAC's tested could be shown (even if image is provided from elsewhere to avoid warranty issues), so we can see which have the best parts. So when two DAC/AMP's are so close in measurements and price etc, that one can see which parts they use and determine if one could wear out slower etc.
 

Kane1972

Active Member
Joined
Dec 11, 2018
Messages
298
Likes
103
Do you have any links to research from the last decade, to support your assertions?

Somewhere in all of your posts, you claimed that SMSL M500 is “fake balanced”, what are you basing this on?

I guess you’re also claiming that the M500 suffers from jitter, which you can somehow hear? Do you have any data or widely accepted testing methodologies to support that?

I don’t really care about SMSL or Topping, at this level of performance it’s all about utility for me. But if you’re going to claim one DAC, which measurements show is audibly transparent, sounds worse than another DAC, which is also transparent, I’d like to see some kind of objective, measurable data to show this. Quite frankly, one paper from 1990 isn’t going to cut it, and this goes for any scientific discipline, we don’t need to meander from theory to theory or wax nostalgia, let’s stick to some tangible data.

I just want to say that the data being 30 years old is irrelevant unless you can produce newer data that contradicts it or disproves it. I mean Nyquist Theory is how old now, but that does not make it untrue.
 

NielsMayer

Active Member
Joined
May 31, 2019
Messages
102
Likes
66
Location
Newport Beach, CA
The clocks on the DAC are for the USB section. If you're concerned about jitter, use the USB interface, as that is what was measured to have low jitter.

IMHO and contrary to the perpetual disinfo you get from this site, all the other inputs do not "reclock" -- jitter in, garbage out. Reclocking is in and of itself potentially problematic, although there are claims that a "dual PLL" design fixes such issues. I have not seen a consumer DAC with this feature other than the ADI-2 "steadyclock" (TBD -- does it suffer from the problems alluded to in the paper about dual PLL reclocking i posted previously).\

Does the DX7Pro /M500/etc have a "steadyclock" -- if it did it would have an FPGA and a bunch of other crap and Topping or SMSL would have pretty marketing pictures and statements about it as a feature.

On pondering the role of the third 100Mhz fancy "femptosecond" clock, I'm pretty sure now the DX7Pro does not literally "reclock" but it does have a simple single-PLL circuit to de-jitter the SPDIF and Optical inputs. The other two crystal oscillators support sampling rates in multiples of 44.1k and 48k over the USB interface.

See: https://www.audiosciencereview.com/...c-and-headphone-amp-reviewed.9446/post-262644

This standard way of doing an SPDIF/Optical interface gives some jitter immunity, although it is disputed that single phase lock loop-based jitter reduction is "bit perfect" or without its own artefacts. The fact that ADI2 uses an expensive FPGA to implement something more special than what would be available in a cheap off the shelf chip like WM8804/8805 suggests they're doing something a lot fancier than a single PLL in their "steadyclock" implementation (it should alert you that they were willing to spend big $$$ on low-jitter clocking, and still come up with a better sounding DAC even with non SOTA DAC chip, b/c that's how important jitter is to sound quality improvement). Perhaps it is their version of the dual PLL design from AXON or something to address the single PLL shortcomings and the errors it introduces:
https://s3t.it/data/uploads/docs/di...-in-high-resolution-digital-audio-systems.pdf

Why Jitter matters in high resolution digital audio systems
A description of jitter analyses and jitter reduction in a 24bit/96k Broadcast 4 channel D/A converter.
Peter Schut Axon Digital Design BV

"Several plots of the high-resolution jitter analyzer used by Axon Digital Design will show how both data induced, and interface induced jitter artifacts, work their way through normal single PLL clock recovery circuits. Jitter in the D/A process can lower the resolution in the reconstructed analog domain to levels that are clearly audible and demonstrate to every audio engineer the harm to system integrity and system transparency.

Clock Jitter

The jitter responsible for the loss of resolution and distortion in the analog reconstructed signal is clock jitter. This clock jitter is either the wordclock or masterclock of the D/A converter chip. Depending on the conversion principle used by the actual converter, either the masterclock or wordclock needs to be jitter free. The jitter measured at this point is the timing deviation of the transitions compared to an ideal clock. These timing variations are divided into a jitter frequency and amplitude. Examining the eye pattern of these clocks with an oscilloscope can tell you something of the peak to peak value, but gives you no information of the jitter frequency. Using an oscilloscope for jitter amplitudes lower than 1ns is almost impossible. So we need a dedicated jitter analyzer. The unit Axon is using has an intrinsic jitter of 0.4 ps RMS for a clock frequency of 12.288 MHz (=256 x 48 kHz) and 1.2 ps for 192 kHz (=4 x 48 kHz). The theoretical degradation for high frequencies (>5kHz) is shown in table1. This table tells nothing of the audibility of the jitter present, just the measurable artifact that jitter has on discrete frequencies. If we look at the rise in noise floor we get the values shown in table 2. Rev. 1
jitter 8ps 16ps 32ps 64ps 128ps 256ps 05ns 1ns 2ns 4ns
Resolution in bits 20 19 18 17 16 15 14 13 12 11
Table 1: maximum jitter for a given resolution
jitter 1ns 2ns 4ns 8ns 16ns
Noise floor -105dB -97dB -90dB -84dB -79dB
Table 2: maximum jitter for a given noise-floor
High frequency jitter causes more audible degradation than low frequency jitter. High frequency signals are also more degraded by a certain amount of jitter than low frequency signals."
 
Last edited:

NielsMayer

Active Member
Joined
May 31, 2019
Messages
102
Likes
66
Location
Newport Beach, CA
How do we relate the 1 ns figure to dB units reported by Amir?

" If we look at the rise in noise floor we get the values shown in table 2. Rev. 1
jitter 8ps 16ps 32ps 64ps 128ps 256ps 05ns 1ns 2ns 4ns
Resolution in bits 20 19 18 17 16 15 14 13 12 11
Table 1: maximum jitter for a given resolution
jitter 1ns 2ns 4ns 8ns 16ns
Noise floor -105dB -97dB -90dB -84dB -79dB
Table 2: maximum jitter for a given noise-floor" https://s3t.it/data/uploads/docs/di...-in-high-resolution-digital-audio-systems.pdf
 

MediumRare

Major Contributor
Forum Donor
Joined
Sep 17, 2019
Messages
1,949
Likes
2,275
Location
Chicago
" If we look at the rise in noise floor we get the values shown in table 2. Rev. 1
jitter 8ps 16ps 32ps 64ps 128ps 256ps 05ns 1ns 2ns 4ns
Resolution in bits 20 19 18 17 16 15 14 13 12 11
Table 1: maximum jitter for a given resolution
jitter 1ns 2ns 4ns 8ns 16ns
Noise floor -105dB -97dB -90dB -84dB -79dB
Table 2: maximum jitter for a given noise-floor" https://s3t.it/data/uploads/docs/di...-in-high-resolution-digital-audio-systems.pdf
"This table tells nothing of the audibility of the jitter present, just the measurable artifact that jitter has on discrete frequencies."
 

NielsMayer

Active Member
Joined
May 31, 2019
Messages
102
Likes
66
Location
Newport Beach, CA
"This table tells nothing of the audibility of the jitter present, just the measurable artifact that jitter has on discrete frequencies."

Yes and that table is for just one of various different kinds of jitter-induced distortions, with different levels of audibility.

Note that all the 1khz sine and sidebands jitter test shows is that a sine wave of that amplitude and that frequency, and even more importantly, that particular given random phase alignment of said sinewave with the sample rate -- will have the given distortions and nonlinearities visible or visible as sidebands.. Change any and you get different results because jitter distortion is entirely data-dependent. Which, other than showing up big problems, has very little to do with how jitter sounds. (IMHO some of the online sites of how jitter sounds "cherry pick" cases where you can't hear much, as predicted by both theory and experimental results -- this seems to be a common practice among audio-objectivists, as if they were pharma company doing "tobacco science" instead of doing the tests that are specifically known to be problematic, which involve high frequencies, imaging, etc.)

I posted previously a different reference (as well as bibliographic ref to internet-unavailable b/c copyrighted source material) previously about
audibility, in an article that is an excellent overview of the subject, with detailed graphical explanations of concepts).
http://www.audiophilleo.com/docs/Dunn-AP-tn23.pdf
Application and Technical Support for Audio Precision
Jitter Theory
By Julian Dunn
...
Audibility considerations

It is one thing to be able to identify and measure sampling jitter. But how can we tell if there is too much? A recent paper by Eric Benjamin and Benjamin Gannon describes practical research that found the lowest jitter level at which the jitter made a noticeable difference was about 10 ns rms. This was with a high level test sine tone at 17 kHz. With music, none of the subjects found jitter below 20 ns rms to be audible.7 This author has developed a model for jitter audibility based on worst case audio single tone signals including the effects of masking.8 This concluded: “Masking theory suggests that the maximum amount of jitter that will not produce an audible effect is dependent on the jitter spectrum. At low frequencies this level is greater than 100 ns, with a sharp cut-off above 100 Hz to a lower limit of approximately 1 ns (peak) at 500 Hz, falling above this frequency at 6 dB per octave to approximately 10 ps (peak) at 24 kHz, for systems where the audio signal is 120 dB above the threshold of hearing.” In the view of the more recent research, this may be considered to be overcautious. However, the consideration that sampling jitter below 100 Hz will probably be less audible by a factor of more than 40 dB when compared with jitter above 500 Hz is useful when determining the likely relative significance of low- and high-frequency sampling jitter.
 

NielsMayer

Active Member
Joined
May 31, 2019
Messages
102
Likes
66
Location
Newport Beach, CA
Regarding the ESS 9038's built in jitter reduction, all I'm finding is "DPLL" and a firmware setting "DPLL settings" that is related....
http://www.esstech.com/files/7414/5193/1716/ES9038PRO_Product_brief_121715.pdf

Given that "DPLL" probably refers to Dual Phase Locked Loop, it would appear that one the benefits of the 9038Pro's circuitry
is well described in that older paper I earlier referenced that suggested problems with a simple single phase locked loop (e.g. WM8804/8805) and that the 9038PRO solution is a superior one. https://s3t.it/data/uploads/docs/di...-in-high-resolution-digital-audio-systems.pdf

searching for more info on ESS implementation, i see stuff like:
"As you may know the ESS DACs implement a jitter reduction circuit that in principle works similarly to the Vanity's BLL (Buffer Locked Loop), but uses resampling to a fixed oscillator clock domain instead of synchronizing tunable oscillators. A part of this circuit called DPLL has several bandwidth settings which may affect the ability of the DAC to lock onto the incoming digital audio signal. These settings are usually hidden to the user and the DPLL bandwidth is fixed to one of the safe values. One can find a lot of details and experiments with optimal DPLL settings on the internet, let's use this link as an example. If you google "ESS Sabre DPLL settings" or similar you can get a lot of relevant results."

https://hifiduino.wordpress.com/sabre32/ patents
  • Asynchronous sample rate correction by time domain interpolation
  • System and method for digital volume control
  • Device and method for signal processing
  • Asynchronous Sample Rate Converter
  • Low Noise Digital to Analog Converter with Audio Applications
  • Low noise digital to signal interval converter with audio applications


So the 100Mhz crystal circiut is feeding ESS9038 to clock this. In the Topping DX7Pro is it synchronizing the clock to the incoming sample rate, or is it running asynchronously at whatever higher internal rate used by the delta-sigma DA process itself?? Given that is not really "bit perfect" to begin with, i guess the fact that resampling to the internal rate of DAC doesn't matter???
 
Last edited:

LuckyLuke575

Senior Member
Forum Donor
Joined
May 19, 2019
Messages
357
Likes
315
Location
Germany

LuckyLuke575

Senior Member
Forum Donor
Joined
May 19, 2019
Messages
357
Likes
315
Location
Germany
Regarding the ESS 9038's built in jitter reduction, all I'm finding is "DPLL" and a firmware setting "DPLL settings" that is related....
http://www.esstech.com/files/7414/5193/1716/ES9038PRO_Product_brief_121715.pdf

Given that "DPLL" probably refers to Dual Phase Locked Loop, it would appear that one the benefits of the 9038Pro's circuitry
is well described in that older paper I earlier referenced that suggested problems with a simple single phase locked loop (e.g. WM8804/8805) and that the 9038PRO solution is a superior one. https://s3t.it/data/uploads/docs/di...-in-high-resolution-digital-audio-systems.pdf

searching for more info on ESS implementation, i see stuff like:
"As you may know the ESS DACs implement a jitter reduction circuit that in principle works similarly to the Vanity's BLL (Buffer Locked Loop), but uses resampling to a fixed oscillator clock domain instead of synchronizing tunable oscillators. A part of this circuit called DPLL has several bandwidth settings which may affect the ability of the DAC to lock onto the incoming digital audio signal. These settings are usually hidden to the user and the DPLL bandwidth is fixed to one of the safe values. One can find a lot of details and experiments with optimal DPLL settings on the internet, let's use this link as an example. If you google "ESS Sabre DPLL settings" or similar you can get a lot of relevant results."

https://hifiduino.wordpress.com/sabre32/ patents
  • Asynchronous sample rate correction by time domain interpolation
  • System and method for digital volume control
  • Device and method for signal processing
  • Asynchronous Sample Rate Converter
  • Low Noise Digital to Analog Converter with Audio Applications
  • Low noise digital to signal interval converter with audio applications


So the 100Mhz crystal circiut is feeding ESS9038 to clock this. In the Topping DX7Pro is it synchronizing the clock to the incoming sample rate, or is it running asynchronously at whatever higher internal rate used by the delta-sigma DA process itself?? Given that is not really "bit perfect" to begin with, i guess the fact that resampling to the internal rate of DAC doesn't matter???
I don't know if this is a crusade or a meltdown at this point
 

BDWoody

Chief Cat Herder
Moderator
Forum Donor
Joined
Jan 9, 2019
Messages
6,948
Likes
22,627
Location
Mid-Atlantic, USA. (Maryland)

LuckyLuke575

Senior Member
Forum Donor
Joined
May 19, 2019
Messages
357
Likes
315
Location
Germany
We just need more quotes from other people to convince us...clearly...
I'm not convinced at all. The guy must know I'll never be convinced by hogwash.
 

Shoaibexpert

Addicted to Fun and Learning
Joined
Apr 28, 2019
Messages
521
Likes
192
I guess here is the key question to those fortunate to have heared both: Was there any discernable difference in Sound Quality between the DX7 Pro and the M500?
 

MediumRare

Major Contributor
Forum Donor
Joined
Sep 17, 2019
Messages
1,949
Likes
2,275
Location
Chicago
I guess here is the key question to those fortunate to have heared both: Was there any discernable difference in Sound Quality between the DX7 Pro and the M500?
Where in the measurements is a difference you expect to be audible?
 
  • Like
Reactions: Tks

Evgeniy

Active Member
Joined
Aug 10, 2018
Messages
107
Likes
51
Location
Ukraine, Odessa .
So the 100Mhz crystal circiut is feeding ESS9038 to clock this. In the Topping DX7Pro is it synchronizing the clock to the incoming sample rate, or is it running asynchronously at whatever higher internal rate used by the delta-sigma DA process itself?

ESS chips (9018,9028,9038) has ASRC mode, but we don't know, what configuration used in dx7 / dx7pro , M5 and M500.
 
Last edited:

Veri

Master Contributor
Joined
Feb 6, 2018
Messages
9,596
Likes
12,036
Few devices use sync mode cause there's no real drawback to async. Allo Katana uses sync. Okto DAC has SRC off, too. It's definitely the exception..
 
Top Bottom