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Reference ABX hardware design and implementation

All that complexity so one can use an Apple TV??? Why not use a streamer with S/PDIF out and split/repeat that? The moment you put HDMI in there, complexity goes through the roof and technically you need a license to sell it. The source for example wants to exchange EDID and capabilities with the renderer. In your diagram, which would that be? The first or second box? And we have not even touched on HDCP, key exchange, etc. You are basically building the front-end of a dual zone AVR -- not an easy job.
You're jumping ahead a few steps Amir :-). I've asked Erin to review this option.

abx-external-arc-extractor.png
 
I was afraid it was this bad. It is not even "AX."
Yeah I was shocked. I mean it _works_ but it's not at all what you'd expect, and doesn't follow any protocol I've ever heard of. There's a lot of manual bookkeeping required as well. Still, low bar to hurdle!
 
Do you have enough ram to hold say, 10 seconds of audio? If so, that would be a great way to loop on a segment under the control of the ABX comparator. With music constantly changing, by the time you go and play B, you are not in the same place. With software ABX we can do this.
 
Do you have enough ram to hold say, 10 seconds of audio? If so, that would be a great way to loop on a segment under the control of the ABX comparator. With music constantly changing, by the time you go and play B, you are not in the same place. With software ABX we can do this.
Unfortunately not. The pico 2 only has 520KB of RAM, and 10 seconds of audio is ~2.5MB. DSPi is being ported to more powerful MCUs, and I'm deliberately keeping the digital board modular so either a Pico 3 can be popped in when one arrives, or a board with a fancier MCU can be used.

In the meantime since the unit is app controlled, it's possible to manage this manually but it's not ideal.
 
Do you have enough ram to hold say, 10 seconds of audio? If so, that would be a great way to loop on a segment under the control of the ABX comparator. With music constantly changing, by the time you go and play B, you are not in the same place. With software ABX we can do this.
Hmm, there are drop-in replacements for the pico 2 that do have enough capacity though: https://shop.pimoroni.com/products/pimoroni-pico-plus-2?variant=42092668289107

It'd need a fork of the DSPi firmware, but Troy's very helpful in making those maintainable.
 
Nice work with the cards. This will be something completely different. Molding the relays in potting compound will probably reduce the sound if it becomes a problem.
 
Nice work with the cards. This will be something completely different. Molding the relays in potting compound will probably reduce the sound if it becomes a problem.
Thanks! Easy enough to do placement, but routing the analog module is going to be a royal pain. I can go to 6 layers but it shouldn’t be necessary. If anyone has access to something better than freerouting perhaps I can hand them the pcb?
 
If anyone has access to something better than freerouting perhaps I can hand them the pcb?
What's your platform in general? If KiCad 10, I'd volunteer to do some routing, of whatever PCB, once I have proper schematics.
6 Layers, all 35µm, would be my goto standard, no real benefit using anything lesser.
 
TLDR: May I suggest to strongly consider using Groner's and Polak's composite amp instead of the OPA1612 to meet the performance specifications? An alternative would be the AD797 at the cost of several millivolts DC offset. Rational and sources below. Also, amazing project! :)

I think a reference ABX comparator is a very important objective, but the math for the current implementation does not add up.

The goal is -130 dB THD+N and output noise of 0.63 µVrms within the audiobandwidth (20-20k Hz). Let's forego the A-wheighting to make comparison easier. From Post 17, I understand that the current design uses a constant feedback resistor (Rf) and a variable gain resistor (Rg) for 0-12 dB gain.

Now, we can use the datasheet as a lower boundary, since it specifies 3 Vrms instead of the target 4 Vrms output, while also ignoring source impedance and output loading. This gives us:
1. The total load of the feedback network should be larger than 600R, ideally around 2k (Fig. 7). For 12 dB gain, this means Rf >480R, ideally 1k6.
2. The maximum source impedance should be below 600R, ideally 300R (Fig. 8). Thus, Rf <600R.
3. The output noise of 0.63 µVrms equals a feedback resistance of around 1k or less.

As you see, 1 mismatches with 2 and 3. A-wheighting mitigates a bit, since the distortion occurs towards higher frequencies. But when adding in the higher output target and the minimum line load requirement of 2k, which will be in parallel to the feedback network, the results become rough. Essentially, a better output load linearity is needed.

I could think of 2 alternatives to the OPA1612:
1. Groner's and Polak's composite amp. It has basically unmeaserable distortion with the same noise specs. It has already been rebuild and measured at diyaudio. Implementation wise, a small feedback capacitor would be needed to ensure unity gain at 30 MHz, the effect of which should be neglible within the audio band. Note, the OPA211 at the input appears to be an OPA1611 with slightly tighter specs at higher cost.
2. The AD797. According to Samual Groner's op-amp measurements it tolerates a 200R load (measured: -128 dB THD at 7.7 Vrms). However, the larger input bias currents would result in 2.5-15 mV DC offset under AC coupling and 10k input impedance (0.25 / 1.5 µA bias current typ/max). I believe the DC offset target has not been specified yet, and I have no ideas regarding audibility. To me, it sounds like a bit too much tough. For comparison, OPA1612 specifies ~5 times less (0.06/0.25 µA), and OPA211 is slightly better (0.05/0.20 µA).

One additional note, in principle also the external DUT should have an output impedance of 300R or less to ensure input linearity. If not, one could consider bootstrapping the power supply of the input op-amp. I believe @KSTR suggested this already in the other thread - if not I am terrible sorry. Do you have experience with bootstrapping the OPA1612 specifically? It sounds a bit complicated, given that OPA1612 compensation involves a common emitter output stage referenced against the (impedance of) the power supply (Fig. 29). Therefore, unless someone has done this already, I would neglect this issue and use a regulated power supply as discussed prior. Especially, since I expect a well-performing DUT to have a low output impedance anyways.

Let me know, if I missed anything :)

Literature:
https://doi.org/10.17743/jaes.2017.0008 (composite amp publication, PDF can be found via Google)
https://www.diyaudio.com/community/threads/samuel-groners-super-opamp.337866/ (DIYaudio thread containing schematics, implementations, measurements, etc.)
https://www.nanovolt.ch/resources/ic_opamps/pdf/opamp_distortion.pdf (Samual Groner's op-amp distortion measurements)
https://www.ti.com/lit/ds/symlink/opa1612.pdf (OPA1612 datasheet)
https://www.ti.com/lit/ds/symlink/opa211.pdf (OPA211 datasheet)
https://www.analog.com/media/en/technical-documentation/data-sheets/AD797.pdf (AD797 datasheet)
 
A non-inverting Groner-Polak is a bit complicated, you need tracking rails for the master and a tracking reference node for the slave opamp. This is needed to fulfill the design requirement of neither inputs nor output of the master opamp moving with regard to supplies, it is also needed to implement the fast clipping recovery circuit (which we could forgo here).

I would think buffering the 1611 (or 211) with a BUF634/LME49600 should do, plus tracking rails for the opamp (see https://www.proaudiodesignforum.com...anyuk_Electronic_Design_September_11_2008.pdf). That reduces CM distortion with higher impedance sources (but ~1k being the limit), and allows for heavy loading of the composite from the feedback network.
Manual offset trim will most likely be required, given the AC coupling and resulting large current offset contribution from the bias resistor.
 
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DSPi can do ADAT in or out

without adding ports hardware, re-use the TOSlink ones
 
I could think of 2 alternatives to the OPA1612:
3. OPA828 with power buffer. No offset issues, no CM distortion, better EMC. Noise (4nV/rtHz) I would consider low enough to not be an issue.
 
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Secondly, it's clear the Van Alstine device is not really an ABX device. It plays A and B in a random sequence and asks the listener to decide if they heard a difference. The listener can go back to a previous "trial", but each trial is just one signal. That's fine as far as it goes but causes user fatigue in keeping track of the choices made, and doesn't offer a true A/B/X selection during each trial.
Where do you get that from? In the manual (page 9) it says:
Similarly, at any time during the test, you may
press ENTER to change to the ENTER system (A), press INPUT to change to the INPUT system
(B), or press “0” to return to the current random test (X). “A” or “B” are displayed in place of the
random test number when this occurs
Sounds like normal ABX to me.
 
I think it’s the two different versions of the device. They don’t offer the same testing procedures.
 
Well, then the "Where do you get that from?" question still applies :-)
From talking with Erin! I’d forgotten there were two versions a, so my comment may well not apply to Josh’s unit
 
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What's your platform in general? If KiCad 10, I'd volunteer to do some routing, of whatever PCB, once I have proper schematics.
6 Layers, all 35µm, would be my goto standard, no real benefit using anything lesser.
Thanks! The only advantage of 4 layer is it qualifies for JLC economic assembly, which has a much lower per-board setup fee than standard assembly, and no setup fee for basic parts, although a higher per-BOM-line setup fee for extended parts. With the number of different extended parts on the analog board it's a close call on cost anyway, even for a 2-board prototype run, so I agree I should just go to 6 and not worry.

Do you have any thoughts on stackup for this design? +-13V rails go to most places on the board, we've got analog signals that can mostly be shepherded through placement but still need to sometimes be sent to a mux for calibration taps, or otherwise need to cross, so we'll have to escape some of those to another layer. And then a bunch of mainly I2C on the digital side, and some logic level supplies. My provisional thought was:
  • L1: components, mixed signals and short local power
  • L2: gnd
  • L3/L4: power distribution + some routing
  • L5: gnd
  • L6: mixed signals and local power

And yes it's KiCad 10, but the schematics are in Zener language (https://docs.pcb.new/pages/spec), and I haven't yet found a sensible way to turn those into accurate and human-readable versions.
 
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Thanks. So the function was added between Jan 2014 and May 2015 and the models in question (Josh's and Erin's) are from Dec 2021.


Interesting. So the manual is wrong?
Or Erin's using it in "quick blind test mode". It wasn't the biggest part of the conversation so I didn't dig into it much. I will check when I'm next in contact with him.
 
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