What about them? I did not read the Mutec paper. Clocks have to be clean (low-noise, random and deterministic), preferably with fast edges (high slew) or go into good buffer stages (my designs usually used a sinusoidal clock because it was heavily filtered, then I squared it up on-chip), stable (over PVT -- process, voltage, temperature -- and time), and must arrive at the right time. In an interleaved system, if a clock edge arrives at the wrong time, it is the same as an aperture error. At the output the end result is the signal is shifted in time and the right signal at the wrong time is a wrong signal. That is why clock distribution is critical. Some chips include circuits to help align the lock edges using either a master reference (which must still be distributed properly) or on-chip delays or phase shifters to allow designers to synch up the final system. Audio systems get by easily with ps errors; some of the RF systems I worked on required fs accuracy and that was tough.
A cascade implies something different to me than an interleaved system but it may be the same thing to Mutec and others (I don't know). Time interleaving implies successively outputting from each DAC in turn so that could be considered a cascade of outputs; each output must happen at the right time or again you get sampling errors.
