You have mentioned that it does introduce a jitter, but the conversion is transparent for both clock and data?
transparent for digital means that the input and output DATA (and in this case also the clock) is exactly the same. There is no buffering or changing of protocols going on.
Simply put a continuous string of 0's and 1's remains the same but just changes in physical format (light vs voltage in this case)
Isn't the jitter that was introduced due to conversion makes the clock not "transparent"?
No, the data/clock remains the same. Only the edges of the 0 to 1 and 1 to 0 transitions have a bit of jitter in it.
The data and clock 'values' (same digital signal) are not determined at the edges but when the 1 or 0 has 'settled' so halfway during the bitrate.
So both the data/clock value are determined at the dotted line below so jitter does not influence the data.
Of course for this to work a clock inside the receiver has to synchronize with with the clock that is embedded in the received signal in order to retrieve the data.
This is done by detecting the edges of the 1 to 0 or 0 to 1 transitions in the signal.
That will always contain jitter at that point and may or may not move the (dotted) decision point a bit more forward or backward in time.
This kind of depends on how good (stable/adaptive) the 'flywheel' in the PLL is and how much jitter there is.
Synchronizing the clocks is usually done with a PLL (phase locked loop) which controls the receiver clock frequency and matches it to that of the received signal.
This adapts an internal clock to the average of the incoming clock and should and sort of likes like the equivalent of a flywheel. Small variance don't change the decision point much and thus allows jitter to not influence the decision point (where it is decided incoming data is high or low)
After that is done the jitter of the incoming signal is removed by re-clocking to that of a stable quartz clock of the DAC chip.
The 'jitter' that clock has is what determines the 'jitter' of the DAC output and that is 'disconnected' from the jitter in the signal.
Not all DACs do this equally well though but most modern receivers have no problem unless the incoming data is so far degraded that the edge detection is making errors.
I assume that the receiving device reads the timing from input and doesn't re-clock the stream again using its own clock.
The receiving device synchronizes the internal clock with that of the incoming data/clock by looking at the transitions of the incoming signal.
That received clock is not used to clock the DAC samples. There are intermediate steps in the signal processing that remove the jitter from the incoming stream.
How well that is done is receiver dependent.
