Another cross-validation test method：
The SPDIF signal generated by the interface is sent to the decoder.
Which contains the clock and data signals.
There are many modern decoders that correct the clock signals contained in the SPDIF in a variety of ways (such as the GPLL of the GUSTARD X26).
But there are also DAC that don't fix them.
In this test, I used an R2R decoder, which uses the AK4118 SPDIF receiver chip. The entire I2S signal (the signal sent to the decoder chip contains MCLK) comes from the front-end SPDIF signal of the 4118 recovery.
In this architecture, the SPDIF signal will directly affect the I2S signal. The jitter of the SPDIF signal will directly affect the jitter of the I2S signal.
The R2R decoder chip (AD1865) will reflect these jitters on the analog output.
So we can look at the jitter by performing an FFT analysis on the analog output.
The first is the panorama (the lower the horizontal line, the better. As for the vertical line, there should be only one in the middle)
Purple and green are U16. Red is the XMOS in the test chart above.
The vertical magnification of the above picture takes -130dbrA to -160dbrA
10K-12K
The above picture shows a lot of "spikes"
This picture is a good explanation:
