Thanks for the reply.
but that worked for interface 0 but not for interface 2.How would I implement the buffered daisy chain output? Wouldn't that defeat the bit-perfect sync requirement between sides? @TurtlePaul 's advice kind of confirms my fears - I really need both channels in perfect sync.
You would effectively be making your own splitter between the toslink or coax connector and the pico input pin. With toslink receivers being active you probably don't need any buffering - the output of the receiver would directly drive both the pico input and transmitter input. With coax you would need to connect the coax input to a buffer, and the buffer output to the pico input and to a coax output. There are various schematics online using video buffers or 74 series logic buffers. If this seems too complicated then just buy a splitter and use that.
Thanks! I'll have a look. But - are you 100% sure this will result in a zero latency solution?
And which firmware and Console versions are you using?
This is definitely something that I intend to implement eventually. Once the next release is complete and SPDIF input is stable, I will be working on that among other things. I am still testing the new hybrid filter architecture at the moment and really want that to be as robust as possible before making new additions.
Thank you very much for your work! I will be looking at your code in detail this weekend and eventually upstreaming components of it into future commits. The long term plan is not only to have assignable output pins but also assignable input (SPDIF, USB, I2S) and output (SPDIF, I2S) types.
If anything, the I2S clocks will be a little bit noisier than the SPDIF recovered clocks due to the deterministic fractional jitter; especially if the I2S DAC doesn't have a PLL. Otherwise, both outputs are bit identical. Most likely just a bit of placebo here but I'm glad it's working well for you.The enhancement of @giubeppe now fully supports an I2S 4-pin interface. You can now connect not only simple DAC boards, but also more complex digital interface boards (DDCs) that require an external clock signal (MCLK).
In my system, it sounds slightly better (smoother with a wider soundstage) than the simple SPDIF output board and supports 3 parallel outputs simultaneously (SPDIF, Toslink, and AES digital outputs
No latency that matters in the context of left and right speakers - the positioning of your head will cause bigger variation. Propagation delay of a logic buffer is typically measured in nanoseconds, and will be in the datasheet for whatever logic chip you use.
Your link for the Pico 2 W is actually for the case. I bought this Pico 2 W.
Crap. I just fixed it. Yeah that Pico listing works too. Maybe I'll switch to that. Thanks for the sanity check.
Wow. Where do you get the math or algorithms for that? When they first came out, I read a whitepaper and it seemed like black magic to me. Never thought you could implement them on a CPU that has is probably less powerful than a 486-33.SPDIF input is coming along quite nicely. I have managed to implement a very simplistic ASRC that utilizes less than 2% of Core 0. This enables the SPDIF outputs to be driven at the fixed PIO clock and produces a feedback output which can be passed to the USB feedback endpoint. In other words, we now have the ability to mix SPDIF and USB inputs.
Console 1.1.0-beta1 for Windows and DSPi 1.1.1-hotfix for RP2040.
Eh.. the pico 2 CPU is between 10x and 50x faster than an old Intel 486, depending on workload
Particularly, it can do floating point math, which the 486 can’t do in hardware unless you have the DX variant. And even then, it’s no contest.
