How common is "jitter suppression" in DACs?

[tlr]

A common argument I've seen against SPDIF, especially optical TOSLINK, is they sometimes use the incoming data as the clock source, which could potentially have a lot of jitter depending on the source, compared to asynchronous USB DACs which use an internal clock. But I also know some DACs include "jitter suppression" which essentially reclocks the signal using an internal clock. For example from the RME ADI-2 DAC's manual:

The ADI-2 DAC supports sample rates between 44.1 kHz and 768 kHz. Furthermore, RME's SteadyClock FS guarantees exceptional performance in all clock modes. Thanks to a highly efficient jitter suppression, the DA-conversion always operates on highest sonic level, being completely independent from the quality of the incoming clock signal.​

​

How common is this in the current generation of DACs?

 

[Blumlein 88]

Firstly, any SPDIF (coax, AES, Toslink) is going to require recovering the clock from the SPDIF connection. Some gear is better at that than others. Usually jitter will be higher than USB because the local clock on the DAC can be used.

Is that audible? Not likely unless the gear is really horrible. I wouldn't trust a Schiit product to get it right. There are some others than have odd difficulty with it (like an Emotiva UMC200 theater processor). In general it shouldn't be an issue, and certainly not with something as well designed as the RME offering. You couldn't know for certain without some measuring. Usually it will not be an issue.

 

[yummy]

no. depends on analog PLL. and many don't have this section at all. some are chip solution, many don't have it either

 

[tired_guru]

Firstly, any SPDIF (coax, AES, Toslink) is going to require recovering the clock from the SPDIF connection. Some gear is better at that than others. Usually jitter will be higher than USB because the local clock on the DAC can be used.

Is that audible? Not likely unless the gear is really horrible. I wouldn't trust a Schiit product to get it right. There are some others than have odd difficulty with it (like an Emotiva UMC200 theater processor). In general it shouldn't be an issue, and certainly not with something as well designed as the RME offering. You couldn't know for certain without some measuring. Usually it will not be an issue.

Yes it is going to recover the clock, but then, in some projects like AUNE S16, you can have fpga FIFO buffer with reclocking all samples before they go to the dac. I wonder why it is so hard or expensive to do, that this is only dac I know able to do it (now discontinued anyway ; / ). There is nothing more important than isolating galvanically from extremely noisy PC stuff, especially its ground with tons of shit + also being vulnerable for potential ground loops etc

Why not prepare TOSLINK input with FPGA FIFO reclocking stage using here great low phase noise oscillators, then go to the dac and having great combo instead of putting a lot of effort in isolating USB inputs (which not always is well implemented in many dacs) ?

Would love to hear what's Amir explanation/thoughts of this idea.

This is just wrong IMHO and put a lot of users in danger of dropping performance in specific systems when connecting USB, then another external amp to the dac etc. A lot of noise, interferences, ground loops can take place there, especially when one of components is connected to PC with poor isolation (there is also important how many prongs are on plug in, what kind of electric installation is there etc).

This is how the block diagram looks like and how it should be done by all (downside will be limitation of max sampling frequency or DSD ->only some 64 DoP if I recall through optical, fmax I think up to 192kHz (all depends on quality opto electronics used), officially 96k but for me 44,1k and most of people this is like 80-90% of collection and I would prefere this kind of solution, if somebody really needs dsd like 512 or 384k pcm, feel free to use USB then, it is your choice):

Effect of that was obvious - during auditions I was able to get exactly the same sound quality from very old, crap quality players with optical output as when using USB XMOS async input of the dac. But having completely free system of any crap being transmitted through noisy ground of other components or creating unwanted ground loops thus being sure I am listening to max performance of the unit itself without any degradation.

 

[tlr]

in some projects like AUNE S16, you can have fpga FIFO buffer with reclocking all samples before they go to the dac

How’s this different from what the RME ADI-2 does (mentioned in my original post)?

 

[tired_guru]

How’s this different from what the RME ADI-2 does (mentioned in my original post)?

Not 100% sure how it's implemented inside RME, but they don't use external implementation of fifo buffer to gather all samples first from toslink/coaxial and reclock them with own oscillators before passsing to the dac chip. I think RME just uses jitter time domain eliminator in the dac chip itself (every modern dac has this kind of ability, ESS - patented time jitter eliminator but for me it should be done before processing). So signal is passed directly to the dac without any reclocking first (unlike USB where in async mode xmos with extra own oscillators do the job perfectly thus differences between toslink & usb in many dacs regarding jitter). So there can be only jitter removal into some level, depending on the incoming signal. In example of s16, all jitter can be completely removed before passed to the dac chip.

Correct me someone if I am wrong.