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How a DAC operates?

If you like educational videos and as you asked your opening question by mentioning you actually first began to try knowing ADCs, you will like this video made by Shahriar Shahramian on his excellent youtube channel The Signal Path (RF oriented) :


He explains the basics of delta-sigma modulation and ADC, builds one sigma-delta ADC on a breadboard and measures it to show what the maths has predicted. Highly recommended!
 
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Years ago, since I have mathematics formation, I wished to learn general relativity on a formal basis. Not learning how solve problems on this theory but going above the divulgation level and feel the mechanism on the equations

Reminds me of this meme:

math-physics-trojan-horse-v0-m70wp5xmdauc1.jpeg
 
Reminds me of this meme:

View attachment 403669
Scientists at the school, teacher asks “Fast, how much is 2+2?”

Engineer: “Maybe around 4 +- 10^(-7) depending on implementation and instrumental error”

Informatics: “00000000000100 on a 12 floating point unit”

Mathematician: “I don’t know but I proved it converges”
 
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More interested in the basic transformation from transistor bit signals on voltage output than on the spurious phenomenon and its correction, but is a good didactic exposition. Always admired Amir’s and other member dedication to diffuse their knowledge.
I am not sure your question? I, and several others, have designed data converters (ADCs and DACs) for a living, including full-custom (transistor-level) IC designs. But conveying that knowledge is well beyond an Internet forum. If you want to understand the transistor-level circuits, then I can provide some references (pretty old at this point), that walk through the circuits in detail. They do require math, though not as much calculus as general relativity theory.
 
More interested in the basic transformation from transistor bit signals on voltage output than on the spurious phenomenon and its correction, but is a good didactic exposition. Always admired Amir’s and other member dedication to diffuse their knowledge
Start with the basics. ADCs and DACs are possible because of 1940s mathematical understanding of what minimum capability is needed to transfer information in the presence of noise.

Electronic Engineer college students have to learn a vast amount of stuff in three years. They learn this through thousands of hours of lectures, labs, tutorials and reading textbooks. Randomly reading short articles and watching random utube videos would never get you a degree-level knowledge.
 
I am not sure your question? I, and several others, have designed data converters (ADCs and DACs) for a living, including full-custom (transistor-level) IC designs. But conveying that knowledge is well beyond an Internet forum. If you want to understand the transistor-level circuits, then I can provide some references (pretty old at this point), that walk through the circuits in detail. They do require math, though not as much calculus as general relativity theory.
Not in detail, at least not to the point I can build a DAC :)

I know a DAC produce a voltage from a given bit number on a given moment. But how it does it? How it “knows” how much voltage should give?

A couple of years ago I red an article about quartz hand watches: it explained how a quartz fork was tuned to 2^15 Hz harmonic resonance, keeping it without dump with an electromagnet varying at its exact tuning point (which is achieved by feedback on the electromagnet with the fork itself), applying 15 consecutive logic gates to rectify a 01010101… value into double 001100110011… signal with half the frequency till achieving 1 Hz to bring the final seconds, 2^15 Hz being the first power of two over the human audition frequency threshold to avoid the clock to emit any sound…

I definitely can’t built a clock (and excuse me if I am forgot a stage or a value, was years ago) but now I know how it works in a level defined by me.

Since I have nor teachers nor pupils, I will establish myself when my curiosity will be satisfied :cool:
 
Start with the basics. ADCs and DACs are possible because of 1940s mathematical understanding of what minimum capability is needed to transfer information in the presence of noise.

Electronic Engineer college students have to learn a vast amount of stuff in three years. They learn this through thousands of hours of lectures, labs, tutorials and reading textbooks. Randomly reading short articles and watching random utube videos would never get you a degree-level knowledge.
A physicist need more than 6 to learn general relativity and never was intended to be part as an undergraduate program. Nevertheless, today one can find an introductory course of one single semester to capture the whole idea and solving some basic problems.

An engineer should be responsible of building things and not exploding, a curious scientist on other branch could need how some device works depending on what he needs, or what can deep go into the underlying physics.

I know some basic stuff: your beloved Maxwell equations, Fourier analysis, Shannon-Nyquist theorem. How a transistor works, a capacitor, a resistor, a comparator.

I hope with your help and other members can go from “ok, bits enter from one side and voltage change on the other side” to some other extra understanding.

Have faith…
 
Not in detail, at least not to the point I can build a DAC :)

I know a DAC produce a voltage from a given bit number on a given moment. But how it does it? How it “knows” how much voltage should give?

A couple of years ago I red an article about quartz hand watches: it explained how a quartz fork was tuned to 2^15 Hz harmonic resonance, keeping it without dump with an electromagnet varying at its exact tuning point (which is achieved by feedback on the electromagnet with the fork itself), applying 15 consecutive logic gates to rectify a 01010101… value into double 001100110011… signal with half the frequency till achieving 1 Hz to bring the final seconds, 2^15 Hz being the first power of two over the human audition frequency threshold to avoid the clock to emit any sound…

I definitely can’t built a clock (and excuse me if I am forgot a stage or a value, was years ago) but now I know how it works in a level defined by me.

Since I have nor teachers nor pupils, I will establish myself when my curiosity will be satisfied :cool:
I'm going to skip slope, SAR, and delta-sigma designs and stick to basic DAC designs. Following is a very quick hand-waving explanation, all I've time for before church.

Simplistically, the transistors act as switches to provide a quantity of voltage or current to the output buffers (which also use transistors). A bias and divider circuit determines the amount of current or voltage switched by each transistor (often a differential pair of transistors). You can think of an array of weighted current sources/sinks, or a string ("ladder") of resistors from which the transistor switches select the appropriate voltage. A logic (decoder) circuit converts the input word you feed the DAC to signals driving the desired switches.

In a fully-unary current-mode DAC, each switch cell is one lsb, requiring 2^N cells for an N-bit DAC. That is a lot for a high-resolution DAC, but since each cell is just one lsb, they only need match to better than 50%. A binary DAC would weight the cells with the smallest being just 1 lsb, then next 2 lsbs, 4 lsbs, 8 lsbs, and so forth up to the MSB which is weighted (2^N)/2). Thus only N cells are required for an N-bit DAC. The catch is that each cell in the binary DAC must match to full precision, 2^-N, and that is very difficult. Typically DACs are designed with some unit-weighted most-significant bits, and unary lower bits, providing a trade between matching requirements (for precision) and complexity.

A DAC using a resistor ladder can use a similar scheme, ranging from a ladder of 2^N unit resistors to just N resistors that are binarily (power of two) weighted, and the same number of switches. Designs again typically include a combination of unit and weighted resistor values to trade performance and complexity.

With that, the articles other folks have linked, and the articles I linked previously, you can hopefully get an idea how things work.
 
In a fully-unary current-mode DAC, each switch cell is one lsb, requiring 2^N cells for an N-bit DAC. That is a lot for a high-resolution DAC, but since each cell is just one lsb, they only need match to better than 50%. A binary DAC would weight the cells with the smallest being just 1 lsb, then next 2 lsbs, 4 lsbs, 8 lsbs, and so forth up to the MSB which is weighted (2^N)/2). Thus only N cells are required for an N-bit DAC. The catch is that each cell in the binary DAC must match to full precision, 2^-N, and that is very difficult. Typically DACs are designed with some unit-weighted most-significant bits, and unary lower bits, providing a trade between matching requirements (for precision) and complexity
Thank you so much. The article I’m reading uses the example of a balance with powers of 2 increasing weighs to illustrate the process of reducing the unitary weighting 2^N need.

Nice trick!
 
Thank you so much. The article I’m reading uses the example of a balance with powers of 2 increasing weighs to illustrate the process of reducing the unitary weighting 2^N need.

Nice trick!
NP. The article linked below (written many years ago) goes into some of the trades of segmented DAC designs so may prove helpful. It crams a lot into a relatively few paragraphs, fair warning.

 
NP. The article linked below (written many years ago) goes into some of the trades of segmented DAC designs so may prove helpful. It crams a lot into a relatively few paragraphs, fair warning.

Love the introductory phrase, “the magical thing” referred to the DAC. Always thought this kind of things as “magic” even when I arrive to understand them.

In fact, is precisely when I understood how they work when they became more magical, as happened to me when I learned the underlying mechanism of digital watches. Before I considered “vulgar” because of the marketing of Swiss watches industry.
 
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