General concept apply to ANY DAC, so proof /hardware testing was done using "string" DACs.
Having nucleo-stm32G474re I was thinking how to improve uCPU internal DAC's linearity. Typical THD level usually about -70 dB, mostly HD-2.
Internal ADC is not much better, in differential mode it may gets to -75 dB at the best.
So, there is no choice as to follow notch approach, if costly high linearity ADC is not in consideration. And here is an Invention: instead of classic tween-T or similar circuits I use two DDS generators antiphase - 180 degree apart to create a notch filter.
Main frequency reduced at the inverting summing amplifier by 40 dB, so having -75 dB ADC span I can reach -115 dB linear dynamics. (40 dB in initial research, now I changed to 60 dB, getting linearity “floor” -125 dB)
Next, to differentiate distortion - INL & consequently THD of this two DDS synthesizers, I put switchable RC filters on two channels right before they reach a summing point. See simplified circuits below.
The main concept, is that when one DDS has RC LPF attenuator another path includes R-R divider to have the magnitudes close match, within 1% or better. So FFT analysis of the distorted residue (amplified back by 40 dB) consists mostly by content of the DAC that has R-R in its path.
After DSP processing of this residue, INL curve extracted and instantly applied to second part or "correctional DAC". (uCPU has 7 DAC's). DAC-1 paired with DAC-3 and DAC-2 with DAC-4.
Algorithm is Recursive. Means, when linearity of the DAC-1 just improved, correction of DAC-2 begins, using DAC-1 as a “clean reference”. Firstly, DAC-1 was just improved up to DAC-2 + LPF linearity. Secondly, since switches remap LPF back to DAC-1 it’s spectrum getting even more “cleaning”, that is necessary for another side.
Let I put numbers, for example both DAC initially have HD-2 -70 dBc. DAC-1 keeps -70 after R-R divider, but DAC-2 has 6 dB improvement after LPF leg, reaching -76 dBc. At the end of the first cycle, linearity of DAC-1 is improved to this limit, -76 dB. Switching cycles, DAC-1 with LPF reaches -82, but DAC-2 “restores” initial -70. Finishing cycle-2 this value brought up to -82. See table:
In 20-30 seconds (cycles about 1sec), distortion ( linearity ) of both generators reach -90 dBc for HD-2 & HD-3.
Last nuance, is the delay or phase shift that LPF path exhibits. To null out phase mismatch, and keep notch filter perfectly balanced, sine-wave phase must be “shifted” w/o resynthesis. DAC has “fingerprints” distortion directly related to bytes that it converts, and changing data would make correctional tables useless. I write a simple subroutine that may be called phaserotaror.
Using two additional DACs, I do not change any single bit in the data stream to the main two DACs, all correction stream goes to second pairs, in one cycle to DAC-3 and second cycle to DAC-4. Each cycle flip switches interchanging LPF & R-R.
Again to avoid any change in the main bit stream, sine-wave’s "points" are shifted by circular rotation of the array of samples. Fine tuning is done by manipulation DAC’s “start conversion event".
At this stage phaserotator has 0.035 degree resolution on 16 kHz output (168 MHz uCPU).
See video. For demonstration purposes THD-3 was digitally synthesized to -52 & -60 dB.
THD-2 is "intrinsic" as it is. Switching speed is not equal, and could be adjusted.
-52 dB
-60dB
phaserotator
dual SA monitor
Having nucleo-stm32G474re I was thinking how to improve uCPU internal DAC's linearity. Typical THD level usually about -70 dB, mostly HD-2.
Internal ADC is not much better, in differential mode it may gets to -75 dB at the best.
So, there is no choice as to follow notch approach, if costly high linearity ADC is not in consideration. And here is an Invention: instead of classic tween-T or similar circuits I use two DDS generators antiphase - 180 degree apart to create a notch filter.
Main frequency reduced at the inverting summing amplifier by 40 dB, so having -75 dB ADC span I can reach -115 dB linear dynamics. (40 dB in initial research, now I changed to 60 dB, getting linearity “floor” -125 dB)
Next, to differentiate distortion - INL & consequently THD of this two DDS synthesizers, I put switchable RC filters on two channels right before they reach a summing point. See simplified circuits below.
The main concept, is that when one DDS has RC LPF attenuator another path includes R-R divider to have the magnitudes close match, within 1% or better. So FFT analysis of the distorted residue (amplified back by 40 dB) consists mostly by content of the DAC that has R-R in its path.
After DSP processing of this residue, INL curve extracted and instantly applied to second part or "correctional DAC". (uCPU has 7 DAC's). DAC-1 paired with DAC-3 and DAC-2 with DAC-4.
Algorithm is Recursive. Means, when linearity of the DAC-1 just improved, correction of DAC-2 begins, using DAC-1 as a “clean reference”. Firstly, DAC-1 was just improved up to DAC-2 + LPF linearity. Secondly, since switches remap LPF back to DAC-1 it’s spectrum getting even more “cleaning”, that is necessary for another side.
Let I put numbers, for example both DAC initially have HD-2 -70 dBc. DAC-1 keeps -70 after R-R divider, but DAC-2 has 6 dB improvement after LPF leg, reaching -76 dBc. At the end of the first cycle, linearity of DAC-1 is improved to this limit, -76 dB. Switching cycles, DAC-1 with LPF reaches -82, but DAC-2 “restores” initial -70. Finishing cycle-2 this value brought up to -82. See table:
In 20-30 seconds (cycles about 1sec), distortion ( linearity ) of both generators reach -90 dBc for HD-2 & HD-3.
Last nuance, is the delay or phase shift that LPF path exhibits. To null out phase mismatch, and keep notch filter perfectly balanced, sine-wave phase must be “shifted” w/o resynthesis. DAC has “fingerprints” distortion directly related to bytes that it converts, and changing data would make correctional tables useless. I write a simple subroutine that may be called phaserotaror.
Using two additional DACs, I do not change any single bit in the data stream to the main two DACs, all correction stream goes to second pairs, in one cycle to DAC-3 and second cycle to DAC-4. Each cycle flip switches interchanging LPF & R-R.
Again to avoid any change in the main bit stream, sine-wave’s "points" are shifted by circular rotation of the array of samples. Fine tuning is done by manipulation DAC’s “start conversion event".
At this stage phaserotator has 0.035 degree resolution on 16 kHz output (168 MHz uCPU).
See video. For demonstration purposes THD-3 was digitally synthesized to -52 & -60 dB.
THD-2 is "intrinsic" as it is. Switching speed is not equal, and could be adjusted.
-52 dB
-60dB
phaserotator
dual SA monitor
Last edited:
