masterhw
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DSP latency isn’t just a factor of ‘horsepower,’ but is also related to the choice of filters. I know we’re used to faster chip = can do the ‘work’ in less time, but linear phase FIR especially needs a continuous buffer inherent to the design, which adds unavoidable latency.
Dirac and other DSP architectures use mixed phase and minimum phase FIRs to balance this latency, but it’s still not as simple as faster chip = lower latency.
If D&M have implemented Dirac ART competently on SHARC+ embedded chips, I would expect marginal improvement at best even from a supercomputer. Faster chip bringing better DSP is a powerful idea that marketing is probably happy to support, but that doesn’t necessarily make it reality.
Dirac and other DSP architectures use mixed phase and minimum phase FIRs to balance this latency, but it’s still not as simple as faster chip = lower latency.
If D&M have implemented Dirac ART competently on SHARC+ embedded chips, I would expect marginal improvement at best even from a supercomputer. Faster chip bringing better DSP is a powerful idea that marketing is probably happy to support, but that doesn’t necessarily make it reality.