I believe that NXP has an open UAC2 implementation, but the uC officially supporting it cost even more than the XMOS ones.One thing that I was unable to make work is the ES9822 ADC @384KHz, with 49.152MHz MCLK. Everything is by the book (read: ESS datasheet), the ADC should work at 24.576MHz bit clock (and the MCLK divided by 2), 384KHz settings are by no means different than the settings for 96KHz and 192KHz (only different values), there's even a table in the data sheet with the registers settings for each mode (no need to put the ADC in 2x mode for 384KHz).
Doesn't work, the noise floor raises to absurd values (some -70dB). The DAC works beautiful at 384KHz... I gave up until a better (or luckier) detective than myself could identify a solution. This kind of detectivistic work is the only "secret sauce" of any ESS based implementation...
And a side note, as much as I hate the XMOS controllers (from almost every perspective, starting with the weird programming model, documentation that is everywhere and nowhere, licensing model, prices, and ending with the power intake) that's the only option for us mortals. Any other UAC2 solution is a best kept secret, I could rather get some information from the Pentagon than from those manufactures in Asia (CMedia, ComTrue, etc...) while a reliable and complete open source solution on a generic controller like the STMs doesn't really exist, and won't, since UAC3 is around the corner, eliminating most of the UAC2 mess (that is, the interface polling mechanism).
I believe that NXP has an open UAC2 implementation, but the uC officially supporting it cost even more than the XMOS ones.
I could have given your post a "Like", but I will give it more than a "Like" It is a very good post and impressive results, a comment on the last paragraph. "You are so right"It took another PCB iteration, to correct a few things:
- I wrongly placed my bet on the THS4551 differential amplifier for the ADC input; this otherwise excellent chip doesn't take well low loads, and the ES9822 ADC has only some 430 ohm input impedance. The THS4551 was replaced with standard OPA1612 dual op amps, much more tolerant to low loads.
- Some layout changes to improve the I/O balanced symmetry (affecting the 2nd harmonic results).
Still no THD compensations is used, and I concluded once again that the whole compensation is pretty much an useless feature. Let's start with this one:
- After much experimenting, I concluded that the THD compensation, both in the DAC and ADC have nothing to do with the ESS chips process variations; it only compensated for the external circuitry distortions (2nd and 3rd harmonics). What I have noticed while measuring the ADC/DAC analog loop is that I can compensate the ADC distortions by trimming the DAC compensation, and the other way around! This means that any method we would use for compensate for the ADC and DAC distortions would end up with a compromise.
- Anyways, I concluded that it is much more reasonable to keep these corrections at zero, and optimize the analog I/O stages for minimum distortions (so almost nothing has to be corrected). These optimizations include choosing the best op amps (here, OPA1622 for the DAC IV stage and OPA1612 for the ADC input stage), optimizing the layout for super symmetry and using 0.1% or better components to preserve the symmetry (minimizing the 2nd harmonics). As a plus, such optimizations are largely frequency and level independent, which the THD corrections are not.
- Assume we have an ideal sine source with zero distortions and an ideal analyzer with zero residual distortions, and we trim the ADC and DAC THD using these; after the trimming, if we switch to the ADC/DAC analog loop, the results will be much worse than the sum of the trimmed distortions.
- If we trim the ADC and DAC using the analog loop (difficult, since we have two independent variables), then when inserting a DUT in the analog loop the analyzer residual distortions will be larger and essentially unknown.
- This explains why other builders are maintaining that using low tolerance components in the ADC input is not that important; of course it appears so, if you are using the ADC THD compensation to band aid this. The situation is conceptually the same as using a poor open loop amplifier and relying on negative feedback to fix it.
Here are the final REW distortions measurements.
These are the analog loop distortions vs. Level measurements. Input frequency was 1KHz and sampling rate 48KHz. Always recall that no DAC/ADC THD correction was used.
View attachment 228908
- THD+N/SINAD (orange) reaches abut -115dB, and it is clearly noise limited (see the delta between the THD+N and the THD (red)) except close to 0dbFS where the 3rd harmonic (yellow) appears to dominate. This is not unexpected (0dBFS is 4.1Veff). Given there are two uncorrelated noise contributors (the DAC and the ADC) I believe 115dB SINAD is an excellent value. I have the feeling that the ADC is the major noise contributor, but I have no measurements to support this assumption.
- ESS hump. Once again, I concluded that the DAC ESS hump is impossible to avoid completely; all we can do is to minimize it's effect (by offsetting the I/V stage common mode bias, I used an 1V common mode bias). The strategy to lower the I/V stage gain is effective only because it affects the DAC SNR, therefore partially hiding the "hump" in noise. As you can see, all the THD measurements (THD (red), 2nd Harmonic (violet), 3rd Harmonic (yellow) and IMD (light blue)) appear to be affected by the "hump", and it is NOT the CCIF 19+20KHz IMD that is the most "hump" revealing measurement, since IMD values are also affected by noise, but the THD.
- The super symmetry of the I/O stages pays off; barring the hump effect, 2nd harmonics are down to around -140dB (take this number with a bit of salt, there's a rather large incertitude of measurements in this region). Even so, 2nd harmonic is much lower that the 3rd harmonic, which cab be largely attributed to the op amp intrinsic and loading effect (3rd harmonic values are in the ballpark of the op amps data sheet specification).
- Barring the measurements incertitudes,the minimum THD is reached at about -6dBFS and is around -127dB, and the minimum IMD is around -10dBFS and reaches -120dB. I believe these results are very good.
- Finally, the multi tone THD+N follows almost perfectly the THD+N curve, up to about -20dBFS. However, the multi tone clipping level is, according to REW, at about -9dBFS, so this value must shift the multi tone THD+N curve to the right. One to another, I concluded that the THD+N and multi tone THD+N results are, for all practical purposes, identical.
Here's the distortion vs. frequency measurement. Input signal was -9dBFS, from 20Hz to 30KHz, sampling was 192KHz.
View attachment 228913
- As expected, the THD+N is rather flat, since noise dominates the measurements, except to beyond 20KHz, where the harmonics are taking over.
- Again as expected, the analog circuitry symmetrical layout and close tolerances pays off; the 2nd harmonic (grey) is much lower than the 3rd harmonic (yellow), even if we consider the large measurements uncertainty beyond -130dB. This is to say that the measured values in this range should be considered relative rather than absolute. Once again, the 3rd harmonic performance appears to be driven by the op amps; the values are more or less in line with their data sheets. I don't think there are better op amps today, matching all requirements (low distortions, large bandwidth, large current output) than the OPA1622 (DAC I/V stage) and the OPA1612 (ADC input stage).
- Regarding THD (blue) the magic threshold of -120dB is maintained at all frequencies under 20KHz. Make sure you recall that no THD correction "cheating" was used to get these results. With THD correction, I could get a commercially nice dip at 1KHz, while outside this frequency the THD would be larger, due to the asymmetries and poor tolerances. Or save money on parts, and promote the corrected THD dip values as the best thing since sliced bread .
Howdy, your regulator failures with low impedance ceramic caps could be input overshoot on turn on? the capacitor resonates with the circuit trace/leads causing the input voltage to spike. Easily fixed with series resistor, protective diodes won't be fast enough. Could also be stability issues if used on output (too low ESR).
I meant also in series with the input supply but yes some chips are not worth bothering with. My personal favorite was a TI LVDS receiver with no ESD protection where they seemed to randomly fail in transit but never once installed, the mystery was solved when I found the 'reduced ESD protection' footnote.
For prototyping, I stopped using 0402.Gerbers (exactly as sent to JLCPCB) attached. Friendly warning: if you don't have the proper tools and a technician to do the assembly/rework for you (or if you don't have good technician skills like myself ) don't even think about attempting to solder this rather dense 4 layers board. You may easily end up with an expensive pile of junk silicon. Can somebody imagine the size of a board with through hole components ?
I'm planning an even more dense board, with 0402 parts (this is with 0603) and without the configuration pins (which were useful during development and testing). This will be probably 2/3 the area of the current board.