For many class D topologies, the feedback is taken before the output filter, so the total power bandwidth is the lowest between power stage bandwidth and filter bandwidth. Since there is a need to have the lowest fc as possible value for the filter, it happen to always be driver of the amplifier bandwidth.Could you provide an example of this please?
When I look to block diagrams in Hypex white papers & Self amps book, NC400 schematic, BP interview transcripts, and so on - I find the load and the feedback loop connected to a large inductor and large paralleled caps after the power FET's. Both the output and the feedback would be influenced by the filter. I've been unable to find a diagram or schematic with a filter like this only in the feedback loop.
Once you take the feedback at the filter's output, it corresponds to including the filter in the loop. Then the total bandwidth is determined by the poles and zeros from the loop, including the complex pair caused by the filter.