Hi John,
thank you for your detailed explanation. What i am not unterstanding is why the ess chip choose the the values randomly. Would it not be better to choose the value in case of a average value? Should this approach randomize the error? My background is from the digital side, if there are some reason in the analog side a short answer would be enough for me.
Greetings
Fu
Welcome to The World of Analog.
Or at least of data converters, where digital and analog meet, for better or worse...
Not John, but I'll take a shot at it...
Think of each bit source of having its own (random) error value. It is not practical to make them perfect (they are not digital cells but contain analog voltage or current sources of the right, or nearly-right, value). By randomly selecting bit sources at each sample, the individual bit errors are randomized, turning what would otherwise be a correlated (larger) distortion spur into less objectionable random noise.
HTH - Don
p.s. Years ago I designed a 16-bit DAC for a much higher-frequency application. It was a segmented design, with the upper segments unary (unit-value) current sinks and lower bits using an R-2R ladder on top of similar unit sinks. All the current sinks were trimmed using a combination of coarse "fuse" trims followed final "flag" laser trims. It took about two minutes to trim each DAC, an eternity in the production test world. It was truly 16-bit linear and could be clocked at several hundred MHz back almost twenty years ago. It was not cheap.