Good grief. In the video they say that they compiled the same "code" (logic description) and they liked three of them better! Unbelievable. With the same logic generated each time, they thought three sounded different and better? Do they not have any common sense? While they are at it, maybe I should download the updated firmware 12 times. Maybe three of those will sound better than the rest!
They should really write a book on this alternate universe they live in with its own rules.
Verilog compilers can actually be non-deterministic, or so I've heard (supposedly due to random timing of parallel processes), though the output should obviously always be functionally equivalent. If there are significant behavioural differences, they have clearly not specified all constraints properly. Of course, they're most likely imagining it, or simply making it up.
You'd have to buy multiple copies and see which one you like best.
You know it's funny, but this is exactly how code development is done at so many companies. There simply isn't enough bandwidth - people - to run these sessions through a bunch of people beyond the code developer, project manager, and final sign-off - Paul's listening session.
I realize it should be instrumented and run through testing to catch egregious bugs, and such is done at large companies for all kinds of compliance and regression testing. Lots of people and processes get involved. But in the end to cut the final code there is a small close group of people that get it done. That is the only way to get it done in a timely manner.
They didn't mention if the compiles were various combinations of pre-processor, compiler, optimization, and loader switches - which they may have found over time provide better optimized code - but not always better sounding results. There are "standard" optimizations that don't do good things to the final binary in many real-time applications. And, there are indeed variations that work in one build cycle but not in the next. Not to mention the variations from release to release of the build environment.
This is why we never show the internals that go into final code releases anywhere I have worked, it is simply too arcane and messy - frightening even - to the uninitiated. Even the most organized large institutions with the best processes and intentions can end up with a little bit of a "panic" happening before and usually just after a pending firmware/software release.
It is always wise to let the code settle in use for weeks without change before release, but there is always a rush to provide break fixes involved to some clients. And, there are usually late comers looking to push just one more little fix after the code freeze. You have to keep things tight and push back firmly. You can't do that will too many fingers in the pot.
Given Ted's comments on clock timing, I am not at all surprised at their method of sussing out the shipping image.