Hi,
I’m looking to build a usb pcm-r2r ladder headphone amp. 32bit/192kHz linear pcm input (OSX provides transcoding). My background university degree in parallel and distributed systems, along with embedded formal systems, GPU Astro image processing deconvolution using DFT, and I for the last 6 months been involved in quantum computing in a bank (using QFFT). I almost bought a TacT Millenium 20 odd years ago..
However hardware itself I’m a beginner..
My initial thinking design used;
LT3045 (six in parallel) providing 2.5A at 3.3v fed by toroidal with choke full wave rectifier plus a ground circuit rectifier etc
Xmos xu208 usb to i2s (no spdif)
NVE IL715 to decouple i2s and i2c
Artix a7 fpga ddr for fifo and reclocking the i2s stream
CPLD to manage each channel resistor ladder output as a 24bit ladder
Output from the ladder via an active low pass Sallen-Key Bessel filter with RC final low pass filter to ensure top end. The active filter will use TL074 op amps (better characteristics for PWM) plus DC detect and short circuit protection.
AD 9516 as a masterclock for all devices
As I have researched more I now understand a little more about the odd order harmonics and the relationship to square waves; plus the general idea to minimise the them using small transitions, either 100% or 0% duty, centre sample clocking, plus pre-processing.
I understand the need for doubling tolerance for each ladder bit added and the must low noise power and grounds.
I’ve also see a number of implementations including Soekris’s dam1021-12 1% version that seems decent, reading the review here I note that the DIY DAC used a HK TL3045-based power regulator - I would point out that the basic version only comes with two 3045s, a max of 1A but the noise level for the regulator increases over 60% duty. It may explain some of the mains noise.
The Soekris 1% still remains an option rather than building.. I’ve dissected the board picture and it appears to use 4 banks of resistors in a 7bit configuration with each bank using a 74LVC595A programmed by the fpga to set the bits for the ladder and synchronise the pulse against the shared pwm clock. The resistors look like Vishay 0.001% MR10s.
It looks like it’s double banked per channel to double current delivery into the final capacitor before coming out unbalanced, the balanced drivers then take the output. I’d still add an active and passive low pass filter - one didn’t jump out from the image.
I have a couple of questions;
Q1) has anyone used a fgpa based curve fitting when upscaling from sample rate to 8x pwm switching rate?
The likes of Fermilab and CERN fit curves for particle tracks from the detectors using FPGAs with minimal resources. The curve fitting can be used to fill in the upsampled pwm values. Idea being to use the curve to reduce sample transposition sizes reducing the odd harmonics.
A second fgpa could be added as a pipeline upscaler if the main fpga didn’t have enough logic elements.
Q2) anyone taken each bank output, splitting with one side being inverted through a high pass filter, before being summed bank in to the ladder output? The summation cancels the harmonics for the bank output further up the frequency range. Each bank’s are then reducted?
I’m wondering if this technique would reduce the tolerance required for ladder resistors as the number of bits increase.
Any thoughts/wisdom?
I’m looking to build a usb pcm-r2r ladder headphone amp. 32bit/192kHz linear pcm input (OSX provides transcoding). My background university degree in parallel and distributed systems, along with embedded formal systems, GPU Astro image processing deconvolution using DFT, and I for the last 6 months been involved in quantum computing in a bank (using QFFT). I almost bought a TacT Millenium 20 odd years ago..
However hardware itself I’m a beginner..
My initial thinking design used;
LT3045 (six in parallel) providing 2.5A at 3.3v fed by toroidal with choke full wave rectifier plus a ground circuit rectifier etc
Xmos xu208 usb to i2s (no spdif)
NVE IL715 to decouple i2s and i2c
Artix a7 fpga ddr for fifo and reclocking the i2s stream
CPLD to manage each channel resistor ladder output as a 24bit ladder
Output from the ladder via an active low pass Sallen-Key Bessel filter with RC final low pass filter to ensure top end. The active filter will use TL074 op amps (better characteristics for PWM) plus DC detect and short circuit protection.
AD 9516 as a masterclock for all devices
As I have researched more I now understand a little more about the odd order harmonics and the relationship to square waves; plus the general idea to minimise the them using small transitions, either 100% or 0% duty, centre sample clocking, plus pre-processing.
I understand the need for doubling tolerance for each ladder bit added and the must low noise power and grounds.
I’ve also see a number of implementations including Soekris’s dam1021-12 1% version that seems decent, reading the review here I note that the DIY DAC used a HK TL3045-based power regulator - I would point out that the basic version only comes with two 3045s, a max of 1A but the noise level for the regulator increases over 60% duty. It may explain some of the mains noise.
The Soekris 1% still remains an option rather than building.. I’ve dissected the board picture and it appears to use 4 banks of resistors in a 7bit configuration with each bank using a 74LVC595A programmed by the fpga to set the bits for the ladder and synchronise the pulse against the shared pwm clock. The resistors look like Vishay 0.001% MR10s.
It looks like it’s double banked per channel to double current delivery into the final capacitor before coming out unbalanced, the balanced drivers then take the output. I’d still add an active and passive low pass filter - one didn’t jump out from the image.
I have a couple of questions;
Q1) has anyone used a fgpa based curve fitting when upscaling from sample rate to 8x pwm switching rate?
The likes of Fermilab and CERN fit curves for particle tracks from the detectors using FPGAs with minimal resources. The curve fitting can be used to fill in the upsampled pwm values. Idea being to use the curve to reduce sample transposition sizes reducing the odd harmonics.
A second fgpa could be added as a pipeline upscaler if the main fpga didn’t have enough logic elements.
Q2) anyone taken each bank output, splitting with one side being inverted through a high pass filter, before being summed bank in to the ladder output? The summation cancels the harmonics for the bank output further up the frequency range. Each bank’s are then reducted?
I’m wondering if this technique would reduce the tolerance required for ladder resistors as the number of bits increase.
Any thoughts/wisdom?